/********************************************************************
* Copyright (C) 2011-2018 Texas Instruments Incorporated.
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/
/*********************************************************************
* file: cslr_bootcfg.h
*
* Brief: This file contains the Register Description for TCI6634 bootcfg
*
*********************************************************************/
#ifndef CSLR_BOOTCFG_V1_H
#define CSLR_BOOTCFG_V1_H

/* CSL Modification:
 *  The file has been modified from the AUTOGEN file for the following
 *  reasons:-
 *      a) Updated main/pa/ddr3a PLLC definitions
 */


#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>


#ifdef __cplusplus
extern "C" {
#endif

/* Minimum unit = 1 byte */

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 REVISION_REG;
    volatile Uint8 RSVD0[4];
    volatile Uint32 DIE_ID_REG0;
    volatile Uint32 DIE_ID_REG1;
    volatile Uint32 DIE_ID_REG2;
    volatile Uint32 DIE_ID_REG3;
    volatile Uint32 JTAG_ID_REG0;
    volatile Uint8 RSVD1[4];
    volatile Uint32 DEVSTAT;
    volatile Uint8 RSVD2[20];
    volatile Uint32 KICK_REG0;
    volatile Uint32 KICK_REG1;
    volatile Uint32 BOOTADDR_GEM0_REG;
    volatile Uint8 RSVD3[156];
    volatile Uint32 INTR_RAW_STATUS_REG;
    volatile Uint32 INTR_ENABLED_STATUS_REG;
    volatile Uint32 INTR_ENABLE_REG;
    volatile Uint32 INTR_ENABLE_CLR_REG;
    volatile Uint32 EOI_REG;
    volatile Uint32 FAULT_ADDRESS_REG;
    volatile Uint32 FAULT_STATUS_REG;
    volatile Uint32 FAULT_CLEAR_REG;
    volatile Uint8 RSVD4[16];
    volatile Uint32 MAC_ID0;
    volatile Uint32 MAC_ID1;
    volatile Uint8 RSVD5[16];
    volatile Uint32 PCIEVENDORID;
    volatile Uint32 DISABLESTAT;
    volatile Uint32 LRSTNMISTAT_CLR;
    volatile Uint32 RESET_STAT_CLR;
    volatile Uint8 RSVD6[4];
    volatile Uint32 BOOT_COMPLETE;
    volatile Uint32 BOOT_PROGRESS;
    volatile Uint32 RESET_STAT;
    volatile Uint32 LRSTNMISTAT;
    volatile Uint32 DEVCFG;
    volatile Uint32 PWR_STAT;
    volatile Uint32 DSP_DISABLE_CTL;
    volatile Uint8 RSVD7[40];
    volatile Uint32 CLASS0_EFUSE0_REG;
    volatile Uint8 RSVD8[12];
    volatile Uint32 SEN0_0_EFUSE_REG0;
    volatile Uint32 SEN1_0_EFUSE_REG1;
    volatile Uint32 SEN2_0_EFUSE_REG2;
    volatile Uint32 SEN3_0_EFUSE_REG3;
    volatile Uint32 SEN0_1_EFUSE_REG4;
    volatile Uint32 SEN1_1_EFUSE_REG5;
    volatile Uint32 SEN2_1_EFUSE_REG6;
    volatile Uint32 SEN3_1_EFUSE_REG7;
    volatile Uint32 SEN0_2_EFUSE_REG8;
    volatile Uint32 SEN1_2_EFUSE_REG9;
    volatile Uint32 SEN2_2_EFUSE_REG10;
    volatile Uint32 SEN3_2_EFUSE_REG11;
    volatile Uint32 SEN0_3_EFUSE_REG12;
    volatile Uint32 SEN1_3_EFUSE_REG13;
    volatile Uint32 SEN2_3_EFUSE_REG14;
    volatile Uint32 SEN3_3_EFUSE_REG15;
    volatile Uint8 RSVD9[48];
    volatile Uint32 NMIGR_0;
    volatile Uint8 RSVD10[60];
    volatile Uint32 IPCGR0;
    volatile Uint8 RSVD11[28];
    volatile Uint32 IPCGR8;
    volatile Uint32 IPCGR9;
    volatile Uint32 IPCGR10;
    volatile Uint32 IPCGR11;
    volatile Uint8 RSVD12[12];
    volatile Uint32 IPCGRH;
    volatile Uint32 IPCAR0;
    volatile Uint8 RSVD13[28];
    volatile Uint32 IPCAR8;
    volatile Uint32 IPCAR9;
    volatile Uint32 IPCAR10;
    volatile Uint32 IPCAR11;
    volatile Uint8 RSVD14[12];
    volatile Uint32 IPCARH;
    volatile Uint8 RSVD15[60];
    volatile Uint32 TINPSEL_MSB;
    volatile Uint32 TINPSEL;
    volatile Uint32 TOUTSEL;
    volatile Uint32 RSTMUX0;
    volatile Uint8 RSVD16[28];
    volatile Uint32 RSTMUX8;
    volatile Uint32 RSTMUX9;
    volatile Uint32 RSTMUX10;
    volatile Uint32 RSTMUX11;
    volatile Uint8 RSVD17[24];
    volatile Uint32 MAIN_PLL_CTL0;
    volatile Uint32 MAIN_PLL_CTL1;
    volatile Uint32 PASS_PLL_CTL0;
    volatile Uint32 PASS_PLL_CTL1;
    volatile Uint32 DDR3A_PLL_CTL0;
    volatile Uint32 DDR3A_PLL_CTL1;
    volatile Uint8 RSVD18[52];
    volatile Uint32 SECURE_CONTROL;
    volatile Uint8 RSVD19[96];
    volatile Uint32 ARM_ENDIAN_CFG0_0;
    volatile Uint32 ARM_ENDIAN_CFG0_1;
    volatile Uint32 ARM_ENDIAN_CFG0_2;
    volatile Uint8 RSVD20[4];
    volatile Uint32 ARM_ENDIAN_CFG1_0;
    volatile Uint32 ARM_ENDIAN_CFG1_1;
    volatile Uint32 ARM_ENDIAN_CFG1_2;
    volatile Uint8 RSVD21[4];
    volatile Uint32 ARM_ENDIAN_CFG2_0;
    volatile Uint32 ARM_ENDIAN_CFG2_1;
    volatile Uint32 ARM_ENDIAN_CFG2_2;
    volatile Uint8 RSVD22[4];
    volatile Uint32 ARM_ENDIAN_CFG3_0;
    volatile Uint32 ARM_ENDIAN_CFG3_1;
    volatile Uint32 ARM_ENDIAN_CFG3_2;
    volatile Uint8 RSVD23[4];
    volatile Uint32 ARM_ENDIAN_CFG4_0;
    volatile Uint32 ARM_ENDIAN_CFG4_1;
    volatile Uint32 ARM_ENDIAN_CFG4_2;
    volatile Uint8 RSVD24[4];
    volatile Uint32 ARM_ENDIAN_CFG5_0;
    volatile Uint32 ARM_ENDIAN_CFG5_1;
    volatile Uint32 ARM_ENDIAN_CFG5_2;
    volatile Uint8 RSVD25[4];
    volatile Uint32 ARM_ENDIAN_CFG6_0;
    volatile Uint32 ARM_ENDIAN_CFG6_1;
    volatile Uint32 ARM_ENDIAN_CFG6_2;
    volatile Uint8 RSVD26[4];
    volatile Uint32 ARM_ENDIAN_CFG7_0;
    volatile Uint32 ARM_ENDIAN_CFG7_1;
    volatile Uint32 ARM_ENDIAN_CFG7_2;
    volatile Uint8 RSVD27[4];
    volatile Uint32 ARMTBR_TRB0_W0;
    volatile Uint32 ARMTBR_TRB0_W1;
    volatile Uint32 ARMTBR_TRB0_W2;
    volatile Uint32 ARMTBR_TRB0_W3;
    volatile Uint32 ARMTBR_TRB1_W0;
    volatile Uint32 ARMTBR_TRB1_W1;
    volatile Uint32 ARMTBR_TRB1_W2;
    volatile Uint32 ARMTBR_TRB1_W3;
    volatile Uint32 ARMTBR_TRB2_W0;
    volatile Uint32 ARMTBR_TRB2_W1;
    volatile Uint32 ARMTBR_TRB2_W2;
    volatile Uint32 ARMTBR_TRB2_W3;
    volatile Uint8 RSVD28[16];
    volatile Uint32 ARMTBR_SHDW_TRB0_W0;
    volatile Uint32 ARMTBR_SHDW_TRB0_W1;
    volatile Uint32 ARMTBR_SHDW_TRB0_W2;
    volatile Uint32 ARMTBR_SHDW_TRB0_W3;
    volatile Uint32 ARMTBR_SHDW_TRB1_W0;
    volatile Uint32 ARMTBR_SHDW_TRB1_W1;
    volatile Uint32 ARMTBR_SHDW_TRB1_W2;
    volatile Uint32 ARMTBR_SHDW_TRB1_W3;
    volatile Uint32 ARMTBR_SHDW_TRB2_W0;
    volatile Uint32 ARMTBR_SHDW_TRB2_W1;
    volatile Uint32 ARMTBR_SHDW_TRB2_W2;
    volatile Uint32 ARMTBR_SHDW_TRB2_W3;
    volatile Uint8 RSVD29[16];
    volatile Uint32 DBGTBR_TRB0_W0;
    volatile Uint32 DBGTBR_TRB0_W1;
    volatile Uint32 DBGTBR_TRB0_W2;
    volatile Uint32 DBGTBR_TRB0_W3;
    volatile Uint32 DBGTBR_TRB1_W0;
    volatile Uint32 DBGTBR_TRB1_W1;
    volatile Uint32 DBGTBR_TRB1_W2;
    volatile Uint32 DBGTBR_TRB1_W3;
    volatile Uint32 DBGTBR_TRB2_W0;
    volatile Uint32 DBGTBR_TRB2_W1;
    volatile Uint32 DBGTBR_TRB2_W2;
    volatile Uint32 DBGTBR_TRB2_W3;
    volatile Uint8 RSVD30[16];
    volatile Uint32 DBGTBR_SHDW_TRB0_W0;
    volatile Uint32 DBGTBR_SHDW_TRB0_W1;
    volatile Uint32 DBGTBR_SHDW_TRB0_W2;
    volatile Uint32 DBGTBR_SHDW_TRB0_W3;
    volatile Uint32 DBGTBR_SHDW_TRB1_W0;
    volatile Uint32 DBGTBR_SHDW_TRB1_W1;
    volatile Uint32 DBGTBR_SHDW_TRB1_W2;
    volatile Uint32 DBGTBR_SHDW_TRB1_W3;
    volatile Uint32 DBGTBR_SHDW_TRB2_W0;
    volatile Uint32 DBGTBR_SHDW_TRB2_W1;
    volatile Uint32 DBGTBR_SHDW_TRB2_W2;
    volatile Uint32 DBGTBR_SHDW_TRB2_W3;
    volatile Uint8 RSVD31[400];
    volatile Uint32 CHIP_MISC0;
    volatile Uint8 RSVD32[4];
    volatile Uint32 SPARE0;
    volatile Uint32 SPARE1;
    volatile Uint32 SYS_ENDIAN;
    volatile Uint32 PLLLOCK_PINCTL;
    volatile Uint32 PLLLOCK_STAT;
    volatile Uint32 PLLLOCK_EVAL;
    volatile Uint8 RSVD33[12];
    volatile Uint32 TRACE_PINCTL;
    volatile Uint32 SYNCE_PINCTL;
    volatile Uint32 MARGIN3;
    volatile Uint32 USB0_REG0;
    volatile Uint32 USB0_REG1;
    volatile Uint32 USB0_REG2;
    volatile Uint32 USB0_REG3;
    volatile Uint32 USB0_REG4;
    volatile Uint32 USB0_REG5;
    volatile Uint32 USB1_REG0;
    volatile Uint32 USB1_REG1;
    volatile Uint32 USB1_REG2;
    volatile Uint32 USB1_REG3;
    volatile Uint32 USB1_REG4;
    volatile Uint32 USB1_REG5;
    volatile Uint32 USB0_EBC_IN_CTL;
    volatile Uint8 RSVD34[4];
    volatile Uint32 USB1_EBC_IN_CTL;
    volatile Uint8 RSVD35[12];
    volatile Uint32 SCRATCH00;
    volatile Uint32 SCRATCH01;
    volatile Uint32 SCRATCH02;
    volatile Uint32 SCRATCH03;
    volatile Uint32 SCRATCH04;
    volatile Uint32 SCRATCH05;
    volatile Uint32 SCRATCH06;
    volatile Uint32 SCRATCH07;
    volatile Uint32 SCRATCH08;
    volatile Uint32 SCRATCH09;
    volatile Uint32 SCRATCH10;
    volatile Uint32 SCRATCH11;
    volatile Uint32 SCRATCH12;
    volatile Uint32 SCRATCH13;
    volatile Uint32 SCRATCH14;
    volatile Uint32 SCRATCH15;
    volatile Uint8 RSVD36[64];
    volatile Uint32 DSP_SEC_STAT;
    volatile Uint32 DSP_SEC_EN0;
    volatile Uint8 RSVD37[60];
    volatile Uint32 DSP_BOOTADDR0_NS;
    volatile Uint8 RSVD38[952];
    volatile Uint32 LED_CORE_PASSDONE0;
    volatile Uint32 LED_CORE_PASSDONE1;
    volatile Uint8 RSVD39[24];
    volatile Uint32 LED_ARM_BOOTADDR;
    volatile Uint8 RSVD40[12];
    volatile Uint32 LED_GPIO_CLR;
    volatile Uint32 LED_GPIO_CLR1;
    volatile Uint32 LED_GPIO;
    volatile Uint32 LED_GPIO1;
    volatile Uint32 LED_PLLLOCK0;
    volatile Uint32 LED_PLLLOCK1;
    volatile Uint32 LED_CHIP_PASSDONE;
    volatile Uint8 RSVD41[4];
    volatile Uint32 TDIODE;
    volatile Uint32 MARGIN0;
    volatile Uint32 MARGIN1;
    volatile Uint32 MARGIN2;
    volatile Uint32 EFUSE_SECROM_CHKSUM0;
    volatile Uint32 EFUSE_SECROM_CHKSUM1;
    volatile Uint32 EFUSE_SECROM_CHKSUM2;
    volatile Uint32 EFUSE_SECROM_CHKSUM3;
    volatile Uint32 INT_SPARE0;
    volatile Uint32 INT_SPARE1;
    volatile Uint8 RSVD42[4];
    volatile Uint32 CHIP_MISC1;
    volatile Uint32 OBSCLK_CTL;
    volatile Uint8 RSVD43[4];
    volatile Uint32 CHIP_MISC3;
    volatile Uint8 RSVD44[4];
    volatile Uint32 EFUSE_RSVD0;
    volatile Uint32 EFUSE_RSVD1;
    volatile Uint32 EFUSE_RSVD2;
    volatile Uint32 EFUSE_RSVD3;
    volatile Uint32 PWRSWTCH_WKUP_MODE0_0;
    volatile Uint32 PWRSWTCH_WKUP_MODE0_1;
    volatile Uint32 PWRSWTCH_WKUP_MODE1_0;
    volatile Uint32 PWRSWTCH_WKUP_MODE1_1;
    volatile Uint8 RSVD45[4];
    volatile Uint32 DFT_USB0_UTMI_CONTROL;
    volatile Uint32 DFT_USB0_UTMI_OBSERVE;
    volatile Uint32 DFT_USB1_UTMI_CONTROL;
    volatile Uint32 DFT_USB1_UTMI_OBSERVE;
    volatile Uint8 RSVD46[4923];
    volatile Uint32 END_POINT;
} CSL_BootcfgRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* revision_reg */

#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_MASK (0xC0000000u)
#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_REVISION_REG_REV_SCHEME_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_MASK (0x0FFF0000u)
#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_SHIFT (0x00000010u)
#define CSL_BOOTCFG_REVISION_REG_REV_MODULE_RESETVAL (0x00000E84u)

#define CSL_BOOTCFG_REVISION_REG_REV_RTL_MASK (0x0000F800u)
#define CSL_BOOTCFG_REVISION_REG_REV_RTL_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_REVISION_REG_REV_RTL_RESETVAL (0x00000025u)

#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_MASK (0x00000700u)
#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_REVISION_REG_REV_MAJOR_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_MASK (0x000000C0u)
#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_SHIFT (0x00000006u)
#define CSL_BOOTCFG_REVISION_REG_REV_CUSTOM_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_MASK (0x0000003Fu)
#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_REVISION_REG_REV_MINOR_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_REVISION_REG_RESETVAL (0x4E852901u)

/* die_id_reg0 */

#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG0_DIE_ID0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG0_RESETVAL (0x00000000u)

/* die_id_reg1 */

#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG1_DIE_ID1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG1_RESETVAL (0x00000000u)

/* die_id_reg2 */

#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG2_DIE_ID2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG2_RESETVAL (0x00000000u)

/* die_id_reg3 */

#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DIE_ID_REG3_DIE_ID3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DIE_ID_REG3_RESETVAL (0x00000000u)

/* jtag_id_reg0 */

#define CSL_BOOTCFG_JTAG_ID_REG0_LSBFIELD_MASK (0x00000001u)
#define CSL_BOOTCFG_JTAG_ID_REG0_LSBFIELD_SHIFT (0x00000000u)
#define CSL_BOOTCFG_JTAG_ID_REG0_LSBFIELD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_MANUFACTURERID_MASK (0x00000FFEu)
#define CSL_BOOTCFG_JTAG_ID_REG0_MANUFACTURERID_SHIFT (0x00000001u)
#define CSL_BOOTCFG_JTAG_ID_REG0_MANUFACTURERID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_PARTID_MASK (0x0FFFF000u)
#define CSL_BOOTCFG_JTAG_ID_REG0_PARTID_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_JTAG_ID_REG0_PARTID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_VARIANT_MASK (0xF0000000u)
#define CSL_BOOTCFG_JTAG_ID_REG0_VARIANT_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_JTAG_ID_REG0_VARIANT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_JTAG_ID_REG0_RESETVAL (0x00000000u)

/* devstat */

#define CSL_BOOTCFG_DEVSTAT_ARM_AVS_EN_MASK (0x00080000u)
#define CSL_BOOTCFG_DEVSTAT_ARM_AVS_EN_SHIFT (0x00000013u)
#define CSL_BOOTCFG_DEVSTAT_ARM_AVS_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_ARM_AVS_SHARED_MASK (0x00200000u)
#define CSL_BOOTCFG_DEVSTAT_ARM_AVS_SHARED_SHIFT (0x00000015u)
#define CSL_BOOTCFG_DEVSTAT_ARM_AVS_SHARED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_ARM_ENDIAN_MASK (0x00400000u)
#define CSL_BOOTCFG_DEVSTAT_ARM_ENDIAN_SHIFT (0x00000016u)
#define CSL_BOOTCFG_DEVSTAT_ARM_ENDIAN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_AVS_IF_SEL_MASK (0x00060000u)
#define CSL_BOOTCFG_DEVSTAT_AVS_IF_SEL_SHIFT (0x00000011u)
#define CSL_BOOTCFG_DEVSTAT_AVS_IF_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_BIG_ENDIAN_MASK (0x00000001u)
#define CSL_BOOTCFG_DEVSTAT_BIG_ENDIAN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DEVSTAT_BIG_ENDIAN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_BOOT_MODE_MASK (0x0001FFFEu)
#define CSL_BOOTCFG_DEVSTAT_BOOT_MODE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DEVSTAT_BOOT_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_DDR3A_MAP_EN_MASK (0x02000000u)
#define CSL_BOOTCFG_DEVSTAT_DDR3A_MAP_EN_SHIFT (0x00000019u)
#define CSL_BOOTCFG_DEVSTAT_DDR3A_MAP_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_SPARE_BOOT_BIT_MASK (0x00100000u)
#define CSL_BOOTCFG_DEVSTAT_SPARE_BOOT_BIT_SHIFT (0x00000014u)
#define CSL_BOOTCFG_DEVSTAT_SPARE_BOOT_BIT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_TSIP_EN_MASK (0x01800000u)
#define CSL_BOOTCFG_DEVSTAT_TSIP_EN_SHIFT (0x00000017u)
#define CSL_BOOTCFG_DEVSTAT_TSIP_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVSTAT_RESETVAL     (0x00000000u)

/* kick_reg0 */

#define CSL_BOOTCFG_KICK_REG0_KICK0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_KICK_REG0_KICK0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_KICK_REG0_KICK0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_KICK_REG0_RESETVAL   (0x00000000u)

/* kick_reg1 */

#define CSL_BOOTCFG_KICK_REG1_KICK1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_KICK_REG1_KICK1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_KICK_REG1_KICK1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_KICK_REG1_RESETVAL   (0x00000000u)

/* bootaddr_gem0_reg */

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_GEM0_BOOT_RDY_MASK (0x00000001u)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_GEM0_BOOT_RDY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_GEM0_BOOT_RDY_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_BOOTADDR_GEM0_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_BOOTADDR_GEM0_REG_RESETVAL (0x20B00001u)

/* intr_raw_status_reg */



#define CSL_BOOTCFG_INTR_RAW_STATUS_REG_RESETVAL (0x00000000u)

/* intr_enabled_status_reg */



#define CSL_BOOTCFG_INTR_ENABLED_STATUS_REG_RESETVAL (0x00000000u)

/* intr_enable_reg */



#define CSL_BOOTCFG_INTR_ENABLE_REG_RESETVAL (0x00000000u)

/* intr_enable_clr_reg */



#define CSL_BOOTCFG_INTR_ENABLE_CLR_REG_RESETVAL (0x00000000u)

/* eoi_reg */

#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_MASK (0x000000FFu)
#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EOI_REG_EOI_VECTOR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EOI_REG_RESETVAL     (0x00000000u)

/* fault_address_reg */

#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_ADDRESS_REG_FAULT_ADDR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_ADDRESS_REG_RESETVAL (0x00000000u)

/* fault_status_reg */

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_MASK (0x0F000000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_SHIFT (0x00000018u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_ID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_MASK (0x00FF0000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_SHIFT (0x00000010u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_MSTID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_MASK (0x00001E00u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_SHIFT (0x00000009u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_PRIVID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_MASK (0x00000080u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_SHIFT (0x00000007u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_NS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_MASK (0x0000003Fu)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_STATUS_REG_FAULT_TYPE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_STATUS_REG_RESETVAL (0x00000000u)

/* fault_clear_reg */

#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_MASK (0x00000001u)
#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_FAULT_CLEAR_REG_FAULT_CLEAR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_FAULT_CLEAR_REG_RESETVAL (0x00000000u)

/* mac_id0 */

#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAC_ID0_MAC_ID0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAC_ID0_RESETVAL     (0x00000000u)

/* mac_id1 */

#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAC_ID1_MAC_ID1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MAC_ID1_RESETVAL     (0x00000000u)

/* pcievendorid */

#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PCIEVENDORID_PCIEVENDORID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PCIEVENDORID_RESETVAL (0x00000000u)

/* disablestat */

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU0_MASK (0x00000100u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU0_SHIFT (0x00000008u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU1_MASK (0x00000200u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU1_SHIFT (0x00000009u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU2_MASK (0x00000400u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU3_MASK (0x00000800u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU3_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CPU3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CRYPTO_4_MASK (0x00002000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CRYPTO_4_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_CRYPTO_4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM0_5_MASK (0x00000001u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM0_5_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_GEM0_5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_PCIE1_16_MASK (0x00080000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_PCIE1_16_SHIFT (0x00000013u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_PCIE1_16_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TETRIS_30_MASK (0x00001000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TETRIS_30_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TETRIS_30_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TSIP_3_MASK (0x20000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TSIP_3_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_TSIP_3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB1_27_MASK (0x10000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB1_27_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB1_27_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB_2_MASK (0x08000000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB_2_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_USB_2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_XGE_28_MASK (0x00008000u)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_XGE_28_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_DISABLESTAT_EFUSE_DISABLE_XGE_28_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DISABLESTAT_RESETVAL (0x00000000u)

/* lrstnmistat_clr */

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_MASK (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_MASK (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_MASK (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_MASK (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_4_CLR_MASK (0x00000010u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_4_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_4_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_5_CLR_MASK (0x00000020u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_5_CLR_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_5_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_6_CLR_MASK (0x00000040u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_6_CLR_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_6_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_7_CLR_MASK (0x00000080u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_7_CLR_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_LRESET_STAT_7_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_MASK (0x00000100u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_MASK (0x00000200u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_MASK (0x00000400u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_MASK (0x00000800u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_4_CLR_MASK (0x00001000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_4_CLR_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_4_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_5_CLR_MASK (0x00002000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_5_CLR_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_5_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_6_CLR_MASK (0x00004000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_6_CLR_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_6_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_7_CLR_MASK (0x00008000u)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_7_CLR_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LRSTNMISTAT_CLR_NMI_STAT_7_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_CLR_RESETVAL (0x00000000u)

/* reset_stat_clr */

#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_MASK (0x80000000u)
#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_RESET_STAT_CLR_GRST_STAT_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_MASK (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_0_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_MASK (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_1_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_MASK (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_SHIFT (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_2_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_MASK (0x00000008u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_SHIFT (0x00000003u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_3_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_4_CLR_MASK (0x00000010u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_4_CLR_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_4_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_5_CLR_MASK (0x00000020u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_5_CLR_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_5_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_6_CLR_MASK (0x00000040u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_6_CLR_SHIFT (0x00000006u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_6_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_7_CLR_MASK (0x00000080u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_7_CLR_SHIFT (0x00000007u)
#define CSL_BOOTCFG_RESET_STAT_CLR_LRST_STAT_7_CLR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_CLR_RESETVAL (0x00000000u)

/* boot_complete */













#define CSL_BOOTCFG_BOOT_COMPLETE_RESETVAL (0x000000FEu)

/* boot_progress */

#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_BOOT_PROGRESS_BOOT_PROGRESS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_BOOT_PROGRESS_RESETVAL (0x00000000u)

/* reset_stat */

#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_MASK (0x80000000u)
#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_RESET_STAT_GRST_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_MASK (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_MASK (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_MASK (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_SHIFT (0x00000002u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_MASK (0x00000008u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_SHIFT (0x00000003u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT4_MASK (0x00000010u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT4_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT5_MASK (0x00000020u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT5_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT6_MASK (0x00000040u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT6_SHIFT (0x00000006u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_LRST_STAT7_MASK (0x00000080u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT7_SHIFT (0x00000007u)
#define CSL_BOOTCFG_RESET_STAT_LRST_STAT7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RESET_STAT_RESETVAL  (0x00000000u)

/* lrstnmistat */

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_MASK (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_MASK (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_MASK (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_MASK (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT4_MASK (0x00000010u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT4_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT5_MASK (0x00000020u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT5_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT6_MASK (0x00000040u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT6_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT7_MASK (0x00000080u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT7_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LRSTNMISTAT_LRESET_STAT7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_MASK (0x00000100u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_MASK (0x00000200u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_MASK (0x00000400u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_MASK (0x00000800u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT4_MASK (0x00001000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT4_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT5_MASK (0x00002000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT5_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT6_MASK (0x00004000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT6_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT7_MASK (0x00008000u)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT7_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LRSTNMISTAT_NMI_STAT7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LRSTNMISTAT_RESETVAL (0x00000000u)

/* devcfg */

#define CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_MASK (0x00000018u)
#define CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_DEVCFG_PCIE1_DEV_TYPE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_MASK (0x00000006u)
#define CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DEVCFG_PCIE_DEV_TYPE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_MASK (0x00000001u)
#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DEVCFG_SYSCLKOUTEN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_DEVCFG_RESETVAL      (0x00000001u)

/* pwr_stat */

#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MASK (0x00000002u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_MASK (0x00000004u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_SHIFT (0x00000002u)
#define CSL_BOOTCFG_PWR_STAT_HIBERNATION_MODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_MASK (0xFFFFFFF8u)
#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PWR_STAT_PWR_STAT_GENERAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_STANDBY_MASK (0x00000001u)
#define CSL_BOOTCFG_PWR_STAT_STANDBY_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWR_STAT_STANDBY_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWR_STAT_RESETVAL    (0x00000000u)

/* dsp_disable_ctl */

#define CSL_BOOTCFG_DSP_DISABLE_CTL_DSP_DISABLED_MASK (0x00000001u)
#define CSL_BOOTCFG_DSP_DISABLE_CTL_DSP_DISABLED_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DSP_DISABLE_CTL_DSP_DISABLED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DSP_DISABLE_CTL_RESETVAL (0x00000000u)

/* class0_efuse0_reg */

#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_CLASS0_EFUSE0_REG_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_CLASS0_EFUSE0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_CLASS0_EFUSE0_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CLASS0_EFUSE0_REG_RESETVAL (0x00000000u)

/* sen0_0_efuse_reg0 */

#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_SEN0_0_EFUSE_REG0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_0_EFUSE_REG0_RESETVAL (0x00000000u)

/* sen1_0_efuse_reg1 */

#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_SEN1_0_EFUSE_REG1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_0_EFUSE_REG1_RESETVAL (0x00000000u)

/* sen2_0_efuse_reg2 */

#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_SEN2_0_EFUSE_REG2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_0_EFUSE_REG2_RESETVAL (0x00000000u)

/* sen3_0_efuse_reg3 */

#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_SEN3_0_EFUSE_REG3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_0_EFUSE_REG3_RESETVAL (0x00000000u)

/* sen0_1_efuse_reg4 */

#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_SEN0_1_EFUSE_REG4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_1_EFUSE_REG4_RESETVAL (0x00000000u)

/* sen1_1_efuse_reg5 */

#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_SEN1_1_EFUSE_REG5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_1_EFUSE_REG5_RESETVAL (0x00000000u)

/* sen2_1_efuse_reg6 */

#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_SEN2_1_EFUSE_REG6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_1_EFUSE_REG6_RESETVAL (0x00000000u)

/* sen3_1_efuse_reg7 */

#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_SEN3_1_EFUSE_REG7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_1_EFUSE_REG7_RESETVAL (0x00000000u)

/* sen0_2_efuse_reg8 */

#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_SEN0_2_EFUSE_REG8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_2_EFUSE_REG8_RESETVAL (0x00000000u)

/* sen1_2_efuse_reg9 */

#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_SEN1_2_EFUSE_REG9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_2_EFUSE_REG9_RESETVAL (0x00000000u)

/* sen2_2_efuse_reg10 */

#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_SEN2_2_EFUSE_REG10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_2_EFUSE_REG10_RESETVAL (0x00000000u)

/* sen3_2_efuse_reg11 */

#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_SEN3_2_EFUSE_REG11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_2_EFUSE_REG11_RESETVAL (0x00000000u)

/* sen0_3_efuse_reg12 */

#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_SEN0_3_EFUSE_REG12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN0_3_EFUSE_REG12_RESETVAL (0x00000000u)

/* sen1_3_efuse_reg13 */

#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_SEN1_3_EFUSE_REG13_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN1_3_EFUSE_REG13_RESETVAL (0x00000000u)

/* sen2_3_efuse_reg14 */

#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_SEN2_3_EFUSE_REG14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN2_3_EFUSE_REG14_RESETVAL (0x00000000u)

/* sen3_3_efuse_reg15 */

#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_SEN3_3_EFUSE_REG15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SEN3_3_EFUSE_REG15_RESETVAL (0x00000000u)

/* nmigr_0 */

#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_NMIGR_0_NMIGR_0_REG_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_NMIGR_0_RESETVAL     (0x00000000u)

/* ipcgr0 */

#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_REG_RESETVAL (0x00000000u)

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_MASK (0xFFFFFFF0u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_SHIFT (0x00000004u)
#define CSL_BOOTCFG_IPCGR0_IPCGR0_SRC_RESETVAL (0x00000000u)
#endif

#define CSL_BOOTCFG_IPCGR0_RESETVAL      (0x00000000u)

/* ipcgr8 */

#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR8_IPCGR8_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR8_RESETVAL      (0x00000000u)

/* ipcgr9 */

#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR9_IPCGR9_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR9_RESETVAL      (0x00000000u)

/* ipcgr10 */

#define CSL_BOOTCFG_IPCGR10_IPCGR10_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR10_IPCGR10_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR10_IPCGR10_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR10_RESETVAL     (0x00000000u)

/* ipcgr11 */

#define CSL_BOOTCFG_IPCGR11_IPCGR11_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGR11_IPCGR11_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGR11_IPCGR11_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGR11_RESETVAL     (0x00000000u)

/* ipcgrh */

#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_MASK (0x00000001u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_SHIFT (0x00000000u)
#define CSL_BOOTCFG_IPCGRH_IPCGRH_REG_RESETVAL (0x00000000u)


#define CSL_BOOTCFG_IPCGRH_RESETVAL      (0x00000000u)

/* ipcar0 */


#define CSL_BOOTCFG_IPCAR0_RESETVAL      (0x00000000u)

/* ipcar8 */


#define CSL_BOOTCFG_IPCAR8_RESETVAL      (0x00000000u)

/* ipcar9 */


#define CSL_BOOTCFG_IPCAR9_RESETVAL      (0x00000000u)

/* ipcar10 */


#define CSL_BOOTCFG_IPCAR10_RESETVAL     (0x00000000u)

/* ipcar11 */


#define CSL_BOOTCFG_IPCAR11_RESETVAL     (0x00000000u)

/* ipcarh */


#define CSL_BOOTCFG_IPCARH_RESETVAL      (0x00000000u)

/* tinpsel_msb */

#define CSL_BOOTCFG_TINPSEL_MSB_TINPSEL_MSB_MASK (0x000000FFu)
#define CSL_BOOTCFG_TINPSEL_MSB_TINPSEL_MSB_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL_MSB_TINPSEL_MSB_RESETVAL (0x000000AAu)

#define CSL_BOOTCFG_TINPSEL_MSB_RESETVAL (0x000000AAu)

/* tinpsel */

#define CSL_BOOTCFG_TINPSEL_TINPSEL_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_TINPSEL_TINPSEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TINPSEL_TINPSEL_RESETVAL (0xAAAAAAAAu)

#define CSL_BOOTCFG_TINPSEL_RESETVAL     (0xAAAAAAAAu)

/* toutsel */

#define CSL_BOOTCFG_TOUTSEL_TOUTSEL0_MASK (0x0000001Fu)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TOUTSEL_TOUTSEL1_MASK (0x000003E0u)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_TOUTSEL_TOUTSEL1_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_TOUTSEL_RESETVAL     (0x00000020u)

/* rstmux0 */

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_DELAY0_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_EVSTAT_CLR0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_LOCK0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX0_RSTMUX_OMODE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX0_RESETVAL     (0x00000080u)

/* rstmux8 */

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_DELAY8_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_EVSTAT_CLR8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_LOCK8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX8_RSTMUX_OMODE8_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX8_RESETVAL     (0x00000080u)

/* rstmux9 */

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_DELAY9_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_EVSTAT_CLR9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_LOCK9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX9_RSTMUX_OMODE9_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX9_RESETVAL     (0x00000080u)

/* rstmux10 */

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_DELAY10_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_DELAY10_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_DELAY10_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT10_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT10_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT_CLR10_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT_CLR10_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_EVSTAT_CLR10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_LOCK10_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_LOCK10_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_LOCK10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RSTMUX_OMODE10_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_OMODE10_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX10_RSTMUX_OMODE10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX10_RESETVAL    (0x00000080u)

/* rstmux11 */

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_DELAY11_MASK (0x000000E0u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_DELAY11_SHIFT (0x00000005u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_DELAY11_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT11_MASK (0x00000010u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT11_SHIFT (0x00000004u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT_CLR11_MASK (0x00000200u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT_CLR11_SHIFT (0x00000009u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_EVSTAT_CLR11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_LOCK11_MASK (0x00000001u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_LOCK11_SHIFT (0x00000000u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_LOCK11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RSTMUX_OMODE11_MASK (0x0000000Eu)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_OMODE11_SHIFT (0x00000001u)
#define CSL_BOOTCFG_RSTMUX11_RSTMUX_OMODE11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_RSTMUX11_RESETVAL    (0x00000080u)

/* main_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MASK                     (0x0000003FU)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_SHIFT                    (0U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLD_MAX                      (0x0000003fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MASK                     (0x0007F000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_SHIFT                    (12U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_PLLM_MAX                      (0x0000007fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MASK                    (0xFF000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_SHIFT                   (24U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_RESETVAL                (0x00000005U)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_BWADJ_MAX                     (0x000000ffU)
#endif

#define CSL_BOOTCFG_MAIN_PLL_CTL0_MAIN_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_MAIN_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAIN_PLL_CTL0_MAIN_PLL_CTL0_RESETVAL (0x05000000u)

#define CSL_BOOTCFG_MAIN_PLL_CTL0_RESETVAL (0x05000000u)

/* main_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MASK                    (0x0000000FU)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_SHIFT                   (0U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_BWADJ_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MASK                    (0x00000040U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_SHIFT                   (6U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_ENSAT_MAX                     (0x00000001U)
#endif

#define CSL_BOOTCFG_MAIN_PLL_CTL1_MAIN_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_MAIN_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MAIN_PLL_CTL1_MAIN_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_MAIN_PLL_CTL1_RESETVAL (0x00000040u)

/* pass_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_MASK                     (0x0000003FU)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_SHIFT                    (0U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_RESETVAL                 (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLD_MAX                      (0x0000003fU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_MASK                     (0x0007FFC0U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_SHIFT                    (6U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_RESETVAL                 (0x00000013U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PLLM_MAX                      (0x00001fffU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MASK                    (0x00780000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_SHIFT                   (19U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_CLKOD_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_MASK                    (0x00800000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_SHIFT                   (23U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BYPASS_MAX                     (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_MASK                     (0xFF000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_SHIFT                    (24U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_RESETVAL                 (0x00000009U)
#define CSL_BOOTCFG_PASS_PLL_CTL0_BWADJ_MAX                      (0x000000ffU)
#endif

#define CSL_BOOTCFG_PASS_PLL_CTL0_PASS_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PASS_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PASS_PLL_CTL0_PASS_PLL_CTL0_RESETVAL (0x098804C0u)

#define CSL_BOOTCFG_PASS_PLL_CTL0_RESETVAL (0x098804C0u)

/* pass_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_MASK                    (0x0000000FU)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_SHIFT                   (0U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_BWADJ_MAX                     (0x0000000fU)

#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_MASK                    (0x00000040U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_SHIFT                   (6U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_RESETVAL                (0x00000001U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_ENSAT_MAX                     (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MASK                   (0x00002000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_SHIFT                  (13U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLSEL_MAX                    (0x00000001U)

#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MASK                   (0x00004000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_SHIFT                  (14U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PLLRST_MAX                    (0x00000001U)
#endif

#define CSL_BOOTCFG_PASS_PLL_CTL1_PASS_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PASS_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PASS_PLL_CTL1_PASS_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_PASS_PLL_CTL1_RESETVAL (0x00000040u)

/* ddr3a_pll_ctl0 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_MASK                    (0x0000003FU)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_SHIFT                   (0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_RESETVAL                (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLD_MAX                     (0x0000003fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_MASK                    (0x0007FFC0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_SHIFT                   (6U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_RESETVAL                (0x00000013U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_PLLM_MAX                     (0x00001fffU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_MASK                   (0x00780000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_SHIFT                  (19U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_CLKOD_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_MASK                  (0x00800000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_SHIFT                 (23U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_RESETVAL              (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BYPASS_MAX                   (0x00000001U)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_MASK                   (0xFF000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_SHIFT                  (24U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_RESETVAL               (0x00000009U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_BWADJ_MAX                    (0x000000ffU)
#endif

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_DDR3A_PLL_CTL0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_DDR3A_PLL_CTL0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDR3A_PLL_CTL0_DDR3A_PLL_CTL0_RESETVAL (0x098804C0u)

#define CSL_BOOTCFG_DDR3A_PLL_CTL0_RESETVAL (0x098804C0u)

/* ddr3a_pll_ctl1 */

#ifndef CSL_MODIFICATION
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_MASK                   (0x0000000FU)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_SHIFT                  (0U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_RESETVAL               (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_BWADJ_MAX                    (0x0000000fU)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_MASK                   (0x00000040U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_SHIFT                  (6U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_RESETVAL               (0x00000001U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_ENSAT_MAX                    (0x00000001U)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_MASK                  (0x00004000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_SHIFT                 (14U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_RESETVAL              (0x00000000U)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_PLLRST_MAX                   (0x00000001U)
#endif

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_DDR3A_PLL_CTL1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_DDR3A_PLL_CTL1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DDR3A_PLL_CTL1_DDR3A_PLL_CTL1_RESETVAL (0x00000040u)

#define CSL_BOOTCFG_DDR3A_PLL_CTL1_RESETVAL (0x00000040u)

/* secure_control */

#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SECURE_CONTROL_PBIST_SECURE_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_MASK (0x00000002u)
#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_SECURE_CONTROL_VUSR_SEC_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SECURE_CONTROL_RESETVAL (0x00000000u)

/* arm_endian_cfg0_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_ARMENDIAN_CFG0_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_ARMENDIAN_CFG0_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_ARMENDIAN_CFG0_ADDR_RESETVAL (0x000001C0u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_0_RESETVAL (0x0001C000u)

/* arm_endian_cfg0_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_ARMENDIAN_CFG0_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_ARMENDIAN_CFG0_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_ARMENDIAN_CFG0_SIZE_RESETVAL (0x00000006u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_1_RESETVAL (0x00000006u)

/* arm_endian_cfg0_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_ARMENDIAN_CFG0_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_ARMENDIAN_CFG0_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_ARMENDIAN_CFG0_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG0_2_RESETVAL (0x00000001u)

/* arm_endian_cfg1_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_ARMENDIAN_CFG1_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_ARMENDIAN_CFG1_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_ARMENDIAN_CFG1_ADDR_RESETVAL (0x00000200u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_0_RESETVAL (0x00020000u)

/* arm_endian_cfg1_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_ARMENDIAN_CFG1_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_ARMENDIAN_CFG1_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_ARMENDIAN_CFG1_SIZE_RESETVAL (0x00000009u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_1_RESETVAL (0x00000009u)

/* arm_endian_cfg1_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_ARMENDIAN_CFG1_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_ARMENDIAN_CFG1_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_ARMENDIAN_CFG1_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG1_2_RESETVAL (0x00000001u)

/* arm_endian_cfg2_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_ARMENDIAN_CFG2_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_ARMENDIAN_CFG2_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_ARMENDIAN_CFG2_ADDR_RESETVAL (0x00000BC0u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_0_RESETVAL (0x000BC000u)

/* arm_endian_cfg2_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_ARMENDIAN_CFG2_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_ARMENDIAN_CFG2_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_ARMENDIAN_CFG2_SIZE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_1_RESETVAL (0x00000004u)

/* arm_endian_cfg2_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_ARMENDIAN_CFG2_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_ARMENDIAN_CFG2_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_ARMENDIAN_CFG2_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG2_2_RESETVAL (0x00000001u)

/* arm_endian_cfg3_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_ARMENDIAN_CFG3_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_ARMENDIAN_CFG3_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_ARMENDIAN_CFG3_ADDR_RESETVAL (0x00002100u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_0_RESETVAL (0x00210000u)

/* arm_endian_cfg3_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_ARMENDIAN_CFG3_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_ARMENDIAN_CFG3_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_ARMENDIAN_CFG3_SIZE_RESETVAL (0x00000008u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_1_RESETVAL (0x00000008u)

/* arm_endian_cfg3_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_ARMENDIAN_CFG3_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_ARMENDIAN_CFG3_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_ARMENDIAN_CFG3_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG3_2_RESETVAL (0x00000001u)

/* arm_endian_cfg4_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_ARMENDIAN_CFG4_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_ARMENDIAN_CFG4_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_ARMENDIAN_CFG4_ADDR_RESETVAL (0x0000023Au)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_0_RESETVAL (0x00023A00u)

/* arm_endian_cfg4_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_ARMENDIAN_CFG4_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_ARMENDIAN_CFG4_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_ARMENDIAN_CFG4_SIZE_RESETVAL (0x00000005u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_1_RESETVAL (0x00000005u)

/* arm_endian_cfg4_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_ARMENDIAN_CFG4_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_ARMENDIAN_CFG4_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_ARMENDIAN_CFG4_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG4_2_RESETVAL (0x00000001u)

/* arm_endian_cfg5_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_ARMENDIAN_CFG5_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_ARMENDIAN_CFG5_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_ARMENDIAN_CFG5_ADDR_RESETVAL (0x00002400u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_0_RESETVAL (0x00240000u)

/* arm_endian_cfg5_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_ARMENDIAN_CFG5_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_ARMENDIAN_CFG5_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_ARMENDIAN_CFG5_SIZE_RESETVAL (0x00000006u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_1_RESETVAL (0x00000006u)

/* arm_endian_cfg5_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_ARMENDIAN_CFG5_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_ARMENDIAN_CFG5_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_ARMENDIAN_CFG5_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG5_2_RESETVAL (0x00000001u)

/* arm_endian_cfg6_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_ARMENDIAN_CFG6_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_ARMENDIAN_CFG6_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_ARMENDIAN_CFG6_ADDR_RESETVAL (0x00010000u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_0_RESETVAL (0x01000000u)

/* arm_endian_cfg6_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_ARMENDIAN_CFG6_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_ARMENDIAN_CFG6_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_ARMENDIAN_CFG6_SIZE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_1_RESETVAL (0x00000000u)

/* arm_endian_cfg6_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_ARMENDIAN_CFG6_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_ARMENDIAN_CFG6_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_ARMENDIAN_CFG6_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG6_2_RESETVAL (0x00000001u)

/* arm_endian_cfg7_0 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_ARMENDIAN_CFG7_ADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_ARMENDIAN_CFG7_ADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_ARMENDIAN_CFG7_ADDR_RESETVAL (0x00FFFFFFu)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_0_RESETVAL (0xFFFFFF00u)

/* arm_endian_cfg7_1 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_ARMENDIAN_CFG7_SIZE_MASK (0x0000000Fu)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_ARMENDIAN_CFG7_SIZE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_ARMENDIAN_CFG7_SIZE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_1_RESETVAL (0x00000000u)

/* arm_endian_cfg7_2 */

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_ARMENDIAN_CFG7_DIS_MASK (0x00000001u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_ARMENDIAN_CFG7_DIS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_ARMENDIAN_CFG7_DIS_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_ARM_ENDIAN_CFG7_2_RESETVAL (0x00000001u)

/* armtbr_trb0_w0 */

#define CSL_BOOTCFG_ARMTBR_TRB0_W0_ARMTBR_TRB0_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB0_W0_ARMTBR_TRB0_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB0_W0_ARMTBR_TRB0_W0_RESETVAL (0x027D4000u)

#define CSL_BOOTCFG_ARMTBR_TRB0_W0_RESETVAL (0x027D4000u)

/* armtbr_trb0_w1 */

#define CSL_BOOTCFG_ARMTBR_TRB0_W1_ARMTBR_TRB0_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB0_W1_ARMTBR_TRB0_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB0_W1_ARMTBR_TRB0_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_TRB0_W1_RESETVAL (0x00000000u)

/* armtbr_trb0_w2 */

#define CSL_BOOTCFG_ARMTBR_TRB0_W2_ARMTBR_TRB0_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB0_W2_ARMTBR_TRB0_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB0_W2_ARMTBR_TRB0_W2_RESETVAL (0x00003C00u)

#define CSL_BOOTCFG_ARMTBR_TRB0_W2_RESETVAL (0x00003C00u)

/* armtbr_trb0_w3 */

#define CSL_BOOTCFG_ARMTBR_TRB0_W3_ARMTBR_TRB0_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB0_W3_ARMTBR_TRB0_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB0_W3_ARMTBR_TRB0_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_ARMTBR_TRB0_W3_RESETVAL (0x00000011u)

/* armtbr_trb1_w0 */

#define CSL_BOOTCFG_ARMTBR_TRB1_W0_ARMTBR_TRB1_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB1_W0_ARMTBR_TRB1_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB1_W0_ARMTBR_TRB1_W0_RESETVAL (0x027D4000u)

#define CSL_BOOTCFG_ARMTBR_TRB1_W0_RESETVAL (0x027D4000u)

/* armtbr_trb1_w1 */

#define CSL_BOOTCFG_ARMTBR_TRB1_W1_ARMTBR_TRB1_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB1_W1_ARMTBR_TRB1_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB1_W1_ARMTBR_TRB1_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_TRB1_W1_RESETVAL (0x00000000u)

/* armtbr_trb1_w2 */

#define CSL_BOOTCFG_ARMTBR_TRB1_W2_ARMTBR_TRB1_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB1_W2_ARMTBR_TRB1_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB1_W2_ARMTBR_TRB1_W2_RESETVAL (0x00003C00u)

#define CSL_BOOTCFG_ARMTBR_TRB1_W2_RESETVAL (0x00003C00u)

/* armtbr_trb1_w3 */

#define CSL_BOOTCFG_ARMTBR_TRB1_W3_ARMTBR_TRB1_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB1_W3_ARMTBR_TRB1_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB1_W3_ARMTBR_TRB1_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_ARMTBR_TRB1_W3_RESETVAL (0x00000011u)

/* armtbr_trb2_w0 */

#define CSL_BOOTCFG_ARMTBR_TRB2_W0_ARMTBR_TRB2_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB2_W0_ARMTBR_TRB2_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB2_W0_ARMTBR_TRB2_W0_RESETVAL (0x026204C0u)

#define CSL_BOOTCFG_ARMTBR_TRB2_W0_RESETVAL (0x026204C0u)

/* armtbr_trb2_w1 */

#define CSL_BOOTCFG_ARMTBR_TRB2_W1_ARMTBR_TRB2_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB2_W1_ARMTBR_TRB2_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB2_W1_ARMTBR_TRB2_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_TRB2_W1_RESETVAL (0x00000000u)

/* armtbr_trb2_w2 */

#define CSL_BOOTCFG_ARMTBR_TRB2_W2_ARMTBR_TRB2_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB2_W2_ARMTBR_TRB2_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB2_W2_ARMTBR_TRB2_W2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_TRB2_W2_RESETVAL (0x00000000u)

/* armtbr_trb2_w3 */

#define CSL_BOOTCFG_ARMTBR_TRB2_W3_ARMTBR_TRB2_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_TRB2_W3_ARMTBR_TRB2_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_TRB2_W3_ARMTBR_TRB2_W3_RESETVAL (0x00000081u)

#define CSL_BOOTCFG_ARMTBR_TRB2_W3_RESETVAL (0x00000081u)

/* armtbr_shdw_trb0_w0 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W0_ARMTBR_SHDW_TRB0_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W0_ARMTBR_SHDW_TRB0_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W0_ARMTBR_SHDW_TRB0_W0_RESETVAL (0x027D4000u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W0_RESETVAL (0x027D4000u)

/* armtbr_shdw_trb0_w1 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W1_ARMTBR_SHDW_TRB0_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W1_ARMTBR_SHDW_TRB0_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W1_ARMTBR_SHDW_TRB0_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W1_RESETVAL (0x00000000u)

/* armtbr_shdw_trb0_w2 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W2_ARMTBR_SHDW_TRB0_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W2_ARMTBR_SHDW_TRB0_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W2_ARMTBR_SHDW_TRB0_W2_RESETVAL (0x00003C00u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W2_RESETVAL (0x00003C00u)

/* armtbr_shdw_trb0_w3 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W3_ARMTBR_SHDW_TRB0_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W3_ARMTBR_SHDW_TRB0_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W3_ARMTBR_SHDW_TRB0_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB0_W3_RESETVAL (0x00000011u)

/* armtbr_shdw_trb1_w0 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W0_ARMTBR_SHDW_TRB1_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W0_ARMTBR_SHDW_TRB1_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W0_ARMTBR_SHDW_TRB1_W0_RESETVAL (0x027D4000u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W0_RESETVAL (0x027D4000u)

/* armtbr_shdw_trb1_w1 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W1_ARMTBR_SHDW_TRB1_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W1_ARMTBR_SHDW_TRB1_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W1_ARMTBR_SHDW_TRB1_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W1_RESETVAL (0x00000000u)

/* armtbr_shdw_trb1_w2 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W2_ARMTBR_SHDW_TRB1_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W2_ARMTBR_SHDW_TRB1_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W2_ARMTBR_SHDW_TRB1_W2_RESETVAL (0x00003C00u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W2_RESETVAL (0x00003C00u)

/* armtbr_shdw_trb1_w3 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W3_ARMTBR_SHDW_TRB1_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W3_ARMTBR_SHDW_TRB1_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W3_ARMTBR_SHDW_TRB1_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB1_W3_RESETVAL (0x00000011u)

/* armtbr_shdw_trb2_w0 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W0_ARMTBR_SHDW_TRB2_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W0_ARMTBR_SHDW_TRB2_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W0_ARMTBR_SHDW_TRB2_W0_RESETVAL (0x026204C0u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W0_RESETVAL (0x026204C0u)

/* armtbr_shdw_trb2_w1 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W1_ARMTBR_SHDW_TRB2_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W1_ARMTBR_SHDW_TRB2_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W1_ARMTBR_SHDW_TRB2_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W1_RESETVAL (0x00000000u)

/* armtbr_shdw_trb2_w2 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W2_ARMTBR_SHDW_TRB2_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W2_ARMTBR_SHDW_TRB2_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W2_ARMTBR_SHDW_TRB2_W2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W2_RESETVAL (0x00000000u)

/* armtbr_shdw_trb2_w3 */

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W3_ARMTBR_SHDW_TRB2_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W3_ARMTBR_SHDW_TRB2_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W3_ARMTBR_SHDW_TRB2_W3_RESETVAL (0x00000081u)

#define CSL_BOOTCFG_ARMTBR_SHDW_TRB2_W3_RESETVAL (0x00000081u)

/* dbgtbr_trb0_w0 */

#define CSL_BOOTCFG_DBGTBR_TRB0_W0_DBGTBR_TRB0_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB0_W0_DBGTBR_TRB0_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB0_W0_DBGTBR_TRB0_W0_RESETVAL (0x02850000u)

#define CSL_BOOTCFG_DBGTBR_TRB0_W0_RESETVAL (0x02850000u)

/* dbgtbr_trb0_w1 */

#define CSL_BOOTCFG_DBGTBR_TRB0_W1_DBGTBR_TRB0_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB0_W1_DBGTBR_TRB0_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB0_W1_DBGTBR_TRB0_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_TRB0_W1_RESETVAL (0x00000000u)

/* dbgtbr_trb0_w2 */

#define CSL_BOOTCFG_DBGTBR_TRB0_W2_DBGTBR_TRB0_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB0_W2_DBGTBR_TRB0_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB0_W2_DBGTBR_TRB0_W2_RESETVAL (0x00007C00u)

#define CSL_BOOTCFG_DBGTBR_TRB0_W2_RESETVAL (0x00007C00u)

/* dbgtbr_trb0_w3 */

#define CSL_BOOTCFG_DBGTBR_TRB0_W3_DBGTBR_TRB0_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB0_W3_DBGTBR_TRB0_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB0_W3_DBGTBR_TRB0_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_DBGTBR_TRB0_W3_RESETVAL (0x00000011u)

/* dbgtbr_trb1_w0 */

#define CSL_BOOTCFG_DBGTBR_TRB1_W0_DBGTBR_TRB1_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB1_W0_DBGTBR_TRB1_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB1_W0_DBGTBR_TRB1_W0_RESETVAL (0x02850000u)

#define CSL_BOOTCFG_DBGTBR_TRB1_W0_RESETVAL (0x02850000u)

/* dbgtbr_trb1_w1 */

#define CSL_BOOTCFG_DBGTBR_TRB1_W1_DBGTBR_TRB1_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB1_W1_DBGTBR_TRB1_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB1_W1_DBGTBR_TRB1_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_TRB1_W1_RESETVAL (0x00000000u)

/* dbgtbr_trb1_w2 */

#define CSL_BOOTCFG_DBGTBR_TRB1_W2_DBGTBR_TRB1_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB1_W2_DBGTBR_TRB1_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB1_W2_DBGTBR_TRB1_W2_RESETVAL (0x00007C00u)

#define CSL_BOOTCFG_DBGTBR_TRB1_W2_RESETVAL (0x00007C00u)

/* dbgtbr_trb1_w3 */

#define CSL_BOOTCFG_DBGTBR_TRB1_W3_DBGTBR_TRB1_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB1_W3_DBGTBR_TRB1_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB1_W3_DBGTBR_TRB1_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_DBGTBR_TRB1_W3_RESETVAL (0x00000011u)

/* dbgtbr_trb2_w0 */

#define CSL_BOOTCFG_DBGTBR_TRB2_W0_DBGTBR_TRB2_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB2_W0_DBGTBR_TRB2_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB2_W0_DBGTBR_TRB2_W0_RESETVAL (0x02620540u)

#define CSL_BOOTCFG_DBGTBR_TRB2_W0_RESETVAL (0x02620540u)

/* dbgtbr_trb2_w1 */

#define CSL_BOOTCFG_DBGTBR_TRB2_W1_DBGTBR_TRB2_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB2_W1_DBGTBR_TRB2_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB2_W1_DBGTBR_TRB2_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_TRB2_W1_RESETVAL (0x00000000u)

/* dbgtbr_trb2_w2 */

#define CSL_BOOTCFG_DBGTBR_TRB2_W2_DBGTBR_TRB2_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB2_W2_DBGTBR_TRB2_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB2_W2_DBGTBR_TRB2_W2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_TRB2_W2_RESETVAL (0x00000000u)

/* dbgtbr_trb2_w3 */

#define CSL_BOOTCFG_DBGTBR_TRB2_W3_DBGTBR_TRB2_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_TRB2_W3_DBGTBR_TRB2_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_TRB2_W3_DBGTBR_TRB2_W3_RESETVAL (0x00000081u)

#define CSL_BOOTCFG_DBGTBR_TRB2_W3_RESETVAL (0x00000081u)

/* dbgtbr_shdw_trb0_w0 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W0_DBGTBR_SHDW_TRB0_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W0_DBGTBR_SHDW_TRB0_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W0_DBGTBR_SHDW_TRB0_W0_RESETVAL (0x02850000u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W0_RESETVAL (0x02850000u)

/* dbgtbr_shdw_trb0_w1 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W1_DBGTBR_SHDW_TRB0_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W1_DBGTBR_SHDW_TRB0_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W1_DBGTBR_SHDW_TRB0_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W1_RESETVAL (0x00000000u)

/* dbgtbr_shdw_trb0_w2 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W2_DBGTBR_SHDW_TRB0_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W2_DBGTBR_SHDW_TRB0_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W2_DBGTBR_SHDW_TRB0_W2_RESETVAL (0x00007C00u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W2_RESETVAL (0x00007C00u)

/* dbgtbr_shdw_trb0_w3 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W3_DBGTBR_SHDW_TRB0_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W3_DBGTBR_SHDW_TRB0_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W3_DBGTBR_SHDW_TRB0_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB0_W3_RESETVAL (0x00000011u)

/* dbgtbr_shdw_trb1_w0 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W0_DBGTBR_SHDW_TRB1_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W0_DBGTBR_SHDW_TRB1_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W0_DBGTBR_SHDW_TRB1_W0_RESETVAL (0x02850000u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W0_RESETVAL (0x02850000u)

/* dbgtbr_shdw_trb1_w1 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W1_DBGTBR_SHDW_TRB1_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W1_DBGTBR_SHDW_TRB1_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W1_DBGTBR_SHDW_TRB1_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W1_RESETVAL (0x00000000u)

/* dbgtbr_shdw_trb1_w2 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W2_DBGTBR_SHDW_TRB1_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W2_DBGTBR_SHDW_TRB1_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W2_DBGTBR_SHDW_TRB1_W2_RESETVAL (0x00007C00u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W2_RESETVAL (0x00007C00u)

/* dbgtbr_shdw_trb1_w3 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W3_DBGTBR_SHDW_TRB1_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W3_DBGTBR_SHDW_TRB1_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W3_DBGTBR_SHDW_TRB1_W3_RESETVAL (0x00000011u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB1_W3_RESETVAL (0x00000011u)

/* dbgtbr_shdw_trb2_w0 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W0_DBGTBR_SHDW_TRB2_W0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W0_DBGTBR_SHDW_TRB2_W0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W0_DBGTBR_SHDW_TRB2_W0_RESETVAL (0x02620540u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W0_RESETVAL (0x02620540u)

/* dbgtbr_shdw_trb2_w1 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W1_DBGTBR_SHDW_TRB2_W1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W1_DBGTBR_SHDW_TRB2_W1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W1_DBGTBR_SHDW_TRB2_W1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W1_RESETVAL (0x00000000u)

/* dbgtbr_shdw_trb2_w2 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W2_DBGTBR_SHDW_TRB2_W2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W2_DBGTBR_SHDW_TRB2_W2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W2_DBGTBR_SHDW_TRB2_W2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W2_RESETVAL (0x00000000u)

/* dbgtbr_shdw_trb2_w3 */

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W3_DBGTBR_SHDW_TRB2_W3_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W3_DBGTBR_SHDW_TRB2_W3_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W3_DBGTBR_SHDW_TRB2_W3_RESETVAL (0x00000081u)

#define CSL_BOOTCFG_DBGTBR_SHDW_TRB2_W3_RESETVAL (0x00000081u)

/* chip_misc0 */

#define CSL_BOOTCFG_CHIP_MISC0_AET_MUX_SEL0_MASK (0x00010000u)
#define CSL_BOOTCFG_CHIP_MISC0_AET_MUX_SEL0_SHIFT (0x00000010u)
#define CSL_BOOTCFG_CHIP_MISC0_AET_MUX_SEL0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_AET_MUX_SEL1_MASK (0x00020000u)
#define CSL_BOOTCFG_CHIP_MISC0_AET_MUX_SEL1_SHIFT (0x00000011u)
#define CSL_BOOTCFG_CHIP_MISC0_AET_MUX_SEL1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_CHIP_MISC_MSMC_BLOCK_PARITY_RST_MASK (0x00001000u)
#define CSL_BOOTCFG_CHIP_MISC0_CHIP_MISC_MSMC_BLOCK_PARITY_RST_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_CHIP_MISC0_CHIP_MISC_MSMC_BLOCK_PARITY_RST_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_CHIP_MISC_QM_PRIOR_MASK (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC0_CHIP_MISC_QM_PRIOR_SHIFT (0x00000000u)
#define CSL_BOOTCFG_CHIP_MISC0_CHIP_MISC_QM_PRIOR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_EFUSE_ACTUAL_EN_MASK (0x08000000u)
#define CSL_BOOTCFG_CHIP_MISC0_EFUSE_ACTUAL_EN_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_CHIP_MISC0_EFUSE_ACTUAL_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_EFUSE_REDUND_EN_MASK (0x04000000u)
#define CSL_BOOTCFG_CHIP_MISC0_EFUSE_REDUND_EN_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_CHIP_MISC0_EFUSE_REDUND_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_RAC_AB_DISABLE_MASK (0x00002000u)
#define CSL_BOOTCFG_CHIP_MISC0_RAC_AB_DISABLE_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_CHIP_MISC0_RAC_AB_DISABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_RAC_CD_DISABLE_MASK (0x00004000u)
#define CSL_BOOTCFG_CHIP_MISC0_RAC_CD_DISABLE_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_CHIP_MISC0_RAC_CD_DISABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_RST_ISO_IP_RST_BLK_MASK (0x03F80000u)
#define CSL_BOOTCFG_CHIP_MISC0_RST_ISO_IP_RST_BLK_SHIFT (0x00000013u)
#define CSL_BOOTCFG_CHIP_MISC0_RST_ISO_IP_RST_BLK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_USB1_PME_EN_MASK (0x10000000u)
#define CSL_BOOTCFG_CHIP_MISC0_USB1_PME_EN_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_CHIP_MISC0_USB1_PME_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_USB_PME_EN_MASK (0x00040000u)
#define CSL_BOOTCFG_CHIP_MISC0_USB_PME_EN_SHIFT (0x00000012u)
#define CSL_BOOTCFG_CHIP_MISC0_USB_PME_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC0_RESETVAL  (0x00000000u)

/* spare0 */

#define CSL_BOOTCFG_SPARE0_SPARE0_MASK   (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE0_SPARE0_SHIFT  (0x00000000u)
#define CSL_BOOTCFG_SPARE0_SPARE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE0_RESETVAL      (0x00000000u)

/* spare1 */

#define CSL_BOOTCFG_SPARE1_SPARE1_MASK   (0xFFFFFFFFu)
#define CSL_BOOTCFG_SPARE1_SPARE1_SHIFT  (0x00000000u)
#define CSL_BOOTCFG_SPARE1_SPARE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SPARE1_RESETVAL      (0x00000000u)

/* sys_endian */

#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_MASK (0x00000001u)
#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SYS_ENDIAN_SYS_ENDIAN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_SYS_ENDIAN_RESETVAL  (0x00000001u)

/* plllock_pinctl */

#define CSL_BOOTCFG_PLLLOCK_PINCTL_DBG_PLLLOCK_SELECT_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DBG_PLLLOCK_SELECT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PLLLOCK_PINCTL_DBG_PLLLOCK_SELECT_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_PLLLOCK_PINCTL_RESETVAL (0x00000001u)

/* plllock_stat */

#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_PLLLOCK_STAT_MASK (0x00000002u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_PLLLOCK_STAT_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_STAT_DDR3A_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_MAIN_PLLLOCK_STAT_MASK (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_STAT_MAIN_PLLLOCK_STAT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_MAIN_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_PA_PLLLOCK_STAT_MASK (0x00000008u)
#define CSL_BOOTCFG_PLLLOCK_STAT_PA_PLLLOCK_STAT_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PLLLOCK_STAT_PA_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_PCIE1_PLLLOCK_STAT_MASK (0x00001000u)
#define CSL_BOOTCFG_PLLLOCK_STAT_PCIE1_PLLLOCK_STAT_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_PLLLOCK_STAT_PCIE1_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_PCIE_PLLLOCK_STAT_MASK (0x00000040u)
#define CSL_BOOTCFG_PLLLOCK_STAT_PCIE_PLLLOCK_STAT_SHIFT (0x00000006u)
#define CSL_BOOTCFG_PLLLOCK_STAT_PCIE_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII0_PLLLOCK_STAT_MASK (0x00000200u)
#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII0_PLLLOCK_STAT_SHIFT (0x00000009u)
#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII0_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII1_PLLLOCK_STAT_MASK (0x00000020u)
#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII1_PLLLOCK_STAT_SHIFT (0x00000005u)
#define CSL_BOOTCFG_PLLLOCK_STAT_SGMII1_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_VUSR0_PLLLOCK_STAT_MASK (0x00000080u)
#define CSL_BOOTCFG_PLLLOCK_STAT_VUSR0_PLLLOCK_STAT_SHIFT (0x00000007u)
#define CSL_BOOTCFG_PLLLOCK_STAT_VUSR0_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_XGE_PLLLOCK_STAT_MASK (0x00000400u)
#define CSL_BOOTCFG_PLLLOCK_STAT_XGE_PLLLOCK_STAT_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_PLLLOCK_STAT_XGE_PLLLOCK_STAT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_STAT_RESETVAL (0x00000000u)

/* plllock_eval */

#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_PLLLOCK_EVAL_MASK (0x00000002u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_PLLLOCK_EVAL_SHIFT (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_DDR3A_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_MAIN_PLLLOCK_EVAL_MASK (0x00000001u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_MAIN_PLLLOCK_EVAL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_MAIN_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_PA_PLLLOCK_EVAL_MASK (0x00000008u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PA_PLLLOCK_EVAL_SHIFT (0x00000003u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PA_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_PCIE1_PLLLOCK_EVAL_MASK (0x00001000u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PCIE1_PLLLOCK_EVAL_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PCIE1_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_PCIE_PLLLOCK_EVAL_MASK (0x00000040u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PCIE_PLLLOCK_EVAL_SHIFT (0x00000006u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_PCIE_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII0_PLLLOCK_EVAL_MASK (0x00000200u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII0_PLLLOCK_EVAL_SHIFT (0x00000009u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII0_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII1_PLLLOCK_EVAL_MASK (0x00000020u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII1_PLLLOCK_EVAL_SHIFT (0x00000005u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_SGMII1_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_VUSR0_PLLLOCK_EVAL_MASK (0x00000080u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_VUSR0_PLLLOCK_EVAL_SHIFT (0x00000007u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_VUSR0_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_XGE_PLLLOCK_EVAL_MASK (0x00000400u)
#define CSL_BOOTCFG_PLLLOCK_EVAL_XGE_PLLLOCK_EVAL_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_PLLLOCK_EVAL_XGE_PLLLOCK_EVAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PLLLOCK_EVAL_RESETVAL (0x00000000u)

/* trace_pinctl */

#define CSL_BOOTCFG_TRACE_PINCTL_IO_TRACE_SEL_MASK (0x00007FFFu)
#define CSL_BOOTCFG_TRACE_PINCTL_IO_TRACE_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_TRACE_PINCTL_IO_TRACE_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TRACE_PINCTL_RESETVAL (0x00000000u)

/* synce_pinctl */

#define CSL_BOOTCFG_SYNCE_PINCTL_SYNCE_PINCTL_MASK (0x000000FFu)
#define CSL_BOOTCFG_SYNCE_PINCTL_SYNCE_PINCTL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SYNCE_PINCTL_SYNCE_PINCTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SYNCE_PINCTL_RESETVAL (0x00000000u)

/* margin3 */

#define CSL_BOOTCFG_MARGIN3_DFTREAD1_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN3_DFTREAD1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN3_DFTREAD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN3_RESETVAL     (0x00000000u)

/* usb0_reg0 */

#define CSL_BOOTCFG_USB0_REG0_USB_PHY_RTUNE_ACK_MASK (0x00000800u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_RTUNE_ACK_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_RTUNE_ACK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_PHY_RTUNE_REQ_MASK (0x00000400u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_RTUNE_REQ_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_RTUNE_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_LOOPBACKENB_MASK (0x00000010u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_LOOPBACKENB_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_LOOPBACKENB_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_TEST_POWERDOWN_HSP_MASK (0x00000020u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_TEST_POWERDOWN_HSP_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_TEST_POWERDOWN_HSP_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_TEST_POWERDOWN_SSP_MASK (0x00000040u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_TEST_POWERDOWN_SSP_SHIFT (0x00000006u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_TEST_POWERDOWN_SSP_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_VATESTENB_MASK (0x00000180u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_VATESTENB_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB0_REG0_USB_PHY_TC_VATESTENB_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_TXBITSTUFFEN_MASK (0x00000001u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_TXBITSTUFFEN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_TXBITSTUFFEN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_TXBITSTUFFENH_MASK (0x00000002u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_TXBITSTUFFENH_SHIFT (0x00000001u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_TXBITSTUFFENH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_VBUSVLDEXT_MASK (0x00000004u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_VBUSVLDEXT_SHIFT (0x00000002u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_VBUSVLDEXT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_WORDINTERFACE_MASK (0x00000008u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_WORDINTERFACE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_USB0_REG0_USB_UTMI_WORDINTERFACE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG0_RESETVAL   (0x00000000u)

/* usb0_reg1 */

#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_REQ_MASK (0x00000002u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_REQ_SHIFT (0x00000001u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_SEL_MASK (0x00000004u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_SEL_SHIFT (0x00000002u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_ALT_CLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_EXT_PCLK_REQ_MASK (0x00000008u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_EXT_PCLK_REQ_SHIFT (0x00000003u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_EXT_PCLK_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_REF_CLKREQ_N_MASK (0x00000020u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_REF_CLKREQ_N_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_REF_CLKREQ_N_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_TX2RX_LOOPBK_MASK (0x00000010u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_TX2RX_LOOPBK_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB0_REG1_USB_PIPE_TX2RX_LOOPBK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG1_RESETVAL   (0x00000000u)

/* usb0_reg2 */

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_COMPDISTUNE_MASK (0x00000007u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_COMPDISTUNE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_COMPDISTUNE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_LOS_BIAS_MASK (0x38000000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_LOS_BIAS_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_LOS_BIAS_RESETVAL (0x00000005u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_OTGTUNE_MASK (0x00000070u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_OTGTUNE_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_OTGTUNE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_SQRXTUNE_MASK (0x00000380u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_SQRXTUNE_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_SQRXTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXFSLSTUNE_MASK (0x00003C00u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXFSLSTUNE_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXFSLSTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXHSXVTUNE_MASK (0x0000C000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXHSXVTUNE_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXHSXVTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXPREEMPAMPTUNE_MASK (0x00030000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXPREEMPAMPTUNE_SHIFT (0x00000010u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXPREEMPAMPTUNE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXPREEMPPULSETUNE_MASK (0x00040000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXPREEMPPULSETUNE_SHIFT (0x00000012u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXPREEMPPULSETUNE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXRESTUNE_MASK (0x00180000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXRESTUNE_SHIFT (0x00000013u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXRESTUNE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXRISETUNE_MASK (0x00600000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXRISETUNE_SHIFT (0x00000015u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXRISETUNE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXVREFTUNE_MASK (0x07800000u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXVREFTUNE_SHIFT (0x00000017u)
#define CSL_BOOTCFG_USB0_REG2_USB_PHY_PC_TXVREFTUNE_RESETVAL (0x00000008u)

#define CSL_BOOTCFG_USB0_REG2_RESETVAL   (0x2C28CDC4u)

/* usb0_reg3 */

#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_LOS_LEVEL_MASK (0x0000001Fu)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_LOS_LEVEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_LOS_LEVEL_RESETVAL (0x00000009u)

#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_DEEMPH_3P5DB_MASK (0x000007E0u)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_DEEMPH_3P5DB_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_DEEMPH_3P5DB_RESETVAL (0x00000015u)

#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_DEEMPH_6DB_MASK (0x007E0000u)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_DEEMPH_6DB_SHIFT (0x00000011u)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_DEEMPH_6DB_RESETVAL (0x00000020u)

#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_SWING_FULL_MASK (0x3F800000u)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_SWING_FULL_SHIFT (0x00000017u)
#define CSL_BOOTCFG_USB0_REG3_USB_PHY_PC_PCS_TX_SWING_FULL_RESETVAL (0x00000078u)

#define CSL_BOOTCFG_USB0_REG3_RESETVAL   (0x3C4002A9u)

/* usb0_reg4 */

#define CSL_BOOTCFG_USB0_REG4_USB_CTRL_MISC_DEBUG_EN_MASK (0x00020000u)
#define CSL_BOOTCFG_USB0_REG4_USB_CTRL_MISC_DEBUG_EN_SHIFT (0x00000011u)
#define CSL_BOOTCFG_USB0_REG4_USB_CTRL_MISC_DEBUG_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_COMMONONN_MASK (0x00040000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_COMMONONN_SHIFT (0x00000012u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_COMMONONN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_FSEL_MASK (0x0FC00000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_FSEL_SHIFT (0x00000016u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_FSEL_RESETVAL (0x00000027u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_MPLL_REFSSC_CLK_EN_MASK (0x10000000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_MPLL_REFSSC_CLK_EN_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_MPLL_REFSSC_CLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_OTG_OTGDISABLE_MASK (0x00008000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_OTG_OTGDISABLE_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_OTG_OTGDISABLE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_OTG_VBUSVLDEXTSEL_MASK (0x00010000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_OTG_VBUSVLDEXTSEL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_OTG_VBUSVLDEXTSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_PC_LANE0_TX_TERM_OFFSET_MASK (0x00000F80u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_PC_LANE0_TX_TERM_OFFSET_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_PC_LANE0_TX_TERM_OFFSET_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_PC_TX_VBOOST_LVL_MASK (0x00007000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_PC_TX_VBOOST_LVL_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_PC_TX_VBOOST_LVL_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REF_SSP_EN_MASK (0x20000000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REF_SSP_EN_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REF_SSP_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REF_USE_PAD_MASK (0x40000000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REF_USE_PAD_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REF_USE_PAD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REFCLKSEL_MASK (0x00180000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REFCLKSEL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_REFCLKSEL_RESETVAL (0x00000002u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_RETENABLEN_MASK (0x00200000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_RETENABLEN_SHIFT (0x00000015u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_RETENABLEN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB0_REG4_USB_PHY_SSC_EN_MASK (0x80000000u)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_SSC_EN_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_USB0_REG4_USB_PHY_SSC_EN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB0_REG4_RESETVAL   (0x89F0C000u)

/* usb0_reg5 */

#define CSL_BOOTCFG_USB0_REG5_USB_PHY_MPLL_MULTIPLIER_MASK (0x000FE000u)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_MPLL_MULTIPLIER_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_MPLL_MULTIPLIER_RESETVAL (0x00000019u)

#define CSL_BOOTCFG_USB0_REG5_USB_PHY_REF_CLKDIV2_MASK (0x00100000u)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_REF_CLKDIV2_SHIFT (0x00000014u)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_REF_CLKDIV2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG5_USB_PHY_SSC_RANGE_MASK (0x00000007u)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_SSC_RANGE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_SSC_RANGE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG5_USB_PHY_SSC_REF_CLK_SEL_MASK (0x00001FF0u)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_SSC_REF_CLK_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB0_REG5_USB_PHY_SSC_REF_CLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_REG5_RESETVAL   (0x00032000u)

/* usb1_reg0 */

#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_RTUNE_ACK_MASK (0x00000800u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_RTUNE_ACK_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_RTUNE_ACK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_RTUNE_REQ_MASK (0x00000400u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_RTUNE_REQ_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_RTUNE_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_LOOPBACKENB_MASK (0x00000010u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_LOOPBACKENB_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_LOOPBACKENB_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_TEST_POWERDOWN_HSP_MASK (0x00000020u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_TEST_POWERDOWN_HSP_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_TEST_POWERDOWN_HSP_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_TEST_POWERDOWN_SSP_MASK (0x00000040u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_TEST_POWERDOWN_SSP_SHIFT (0x00000006u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_TEST_POWERDOWN_SSP_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_VATESTENB_MASK (0x00000180u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_VATESTENB_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB1_REG0_USB1_PHY_TC_VATESTENB_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_TXBITSTUFFEN_MASK (0x00000001u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_TXBITSTUFFEN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_TXBITSTUFFEN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_TXBITSTUFFENH_MASK (0x00000002u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_TXBITSTUFFENH_SHIFT (0x00000001u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_TXBITSTUFFENH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_VBUSVLDEXT_MASK (0x00000004u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_VBUSVLDEXT_SHIFT (0x00000002u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_VBUSVLDEXT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_WORDINTERFACE_MASK (0x00000008u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_WORDINTERFACE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_USB1_REG0_USB1_UTMI_WORDINTERFACE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG0_RESETVAL   (0x00000000u)

/* usb1_reg1 */

#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_EN_MASK (0x00000001u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_EN_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_REQ_MASK (0x00000002u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_REQ_SHIFT (0x00000001u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_SEL_MASK (0x00000004u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_SEL_SHIFT (0x00000002u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_ALT_CLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_EXT_PCLK_REQ_MASK (0x00000008u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_EXT_PCLK_REQ_SHIFT (0x00000003u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_EXT_PCLK_REQ_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_REF_CLKREQ_N_MASK (0x00000020u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_REF_CLKREQ_N_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_REF_CLKREQ_N_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_TX2RX_LOOPBK_MASK (0x00000010u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_TX2RX_LOOPBK_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB1_REG1_USB1_PIPE_TX2RX_LOOPBK_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG1_RESETVAL   (0x00000000u)

/* usb1_reg2 */

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_COMPDISTUNE_MASK (0x00000007u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_COMPDISTUNE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_COMPDISTUNE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_LOS_BIAS_MASK (0x38000000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_LOS_BIAS_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_LOS_BIAS_RESETVAL (0x00000005u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_OTGTUNE_MASK (0x00000070u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_OTGTUNE_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_OTGTUNE_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_SQRXTUNE_MASK (0x00000380u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_SQRXTUNE_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_SQRXTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXFSLSTUNE_MASK (0x00003C00u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXFSLSTUNE_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXFSLSTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXHSXVTUNE_MASK (0x0000C000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXHSXVTUNE_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXHSXVTUNE_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXPREEMPAMPTUNE_MASK (0x00030000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXPREEMPAMPTUNE_SHIFT (0x00000010u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXPREEMPAMPTUNE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXPREEMPPULSETUNE_MASK (0x00040000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXPREEMPPULSETUNE_SHIFT (0x00000012u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXPREEMPPULSETUNE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXRESTUNE_MASK (0x00180000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXRESTUNE_SHIFT (0x00000013u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXRESTUNE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXRISETUNE_MASK (0x00600000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXRISETUNE_SHIFT (0x00000015u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXRISETUNE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXVREFTUNE_MASK (0x07800000u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXVREFTUNE_SHIFT (0x00000017u)
#define CSL_BOOTCFG_USB1_REG2_USB1_PHY_PC_TXVREFTUNE_RESETVAL (0x00000008u)

#define CSL_BOOTCFG_USB1_REG2_RESETVAL   (0x2C28CDC4u)

/* usb1_reg3 */

#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_LOS_LEVEL_MASK (0x0000001Fu)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_LOS_LEVEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_LOS_LEVEL_RESETVAL (0x00000009u)

#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_DEEMPH_3P5DB_MASK (0x000007E0u)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_DEEMPH_3P5DB_SHIFT (0x00000005u)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_DEEMPH_3P5DB_RESETVAL (0x00000015u)

#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_DEEMPH_6DB_MASK (0x007E0000u)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_DEEMPH_6DB_SHIFT (0x00000011u)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_DEEMPH_6DB_RESETVAL (0x00000020u)

#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_SWING_FULL_MASK (0x3F800000u)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_SWING_FULL_SHIFT (0x00000017u)
#define CSL_BOOTCFG_USB1_REG3_USB1_PHY_PC_PCS_TX_SWING_FULL_RESETVAL (0x00000078u)

#define CSL_BOOTCFG_USB1_REG3_RESETVAL   (0x3C4002A9u)

/* usb1_reg4 */

#define CSL_BOOTCFG_USB1_REG4_USB1_CTRL_MISC_DEBUG_EN_MASK (0x00020000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_CTRL_MISC_DEBUG_EN_SHIFT (0x00000011u)
#define CSL_BOOTCFG_USB1_REG4_USB1_CTRL_MISC_DEBUG_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_COMMONONN_MASK (0x00040000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_COMMONONN_SHIFT (0x00000012u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_COMMONONN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_FSEL_MASK (0x0FC00000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_FSEL_SHIFT (0x00000016u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_FSEL_RESETVAL (0x00000027u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_MPLL_REFSSC_CLK_EN_MASK (0x10000000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_MPLL_REFSSC_CLK_EN_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_MPLL_REFSSC_CLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_OTG_OTGDISABLE_MASK (0x00008000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_OTG_OTGDISABLE_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_OTG_OTGDISABLE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_OTG_VBUSVLDEXTSEL_MASK (0x00010000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_OTG_VBUSVLDEXTSEL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_OTG_VBUSVLDEXTSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_PC_LANE0_TX_TERM_OFFSET_MASK (0x00000F80u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_PC_LANE0_TX_TERM_OFFSET_SHIFT (0x00000007u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_PC_LANE0_TX_TERM_OFFSET_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_PC_TX_VBOOST_LVL_MASK (0x00007000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_PC_TX_VBOOST_LVL_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_PC_TX_VBOOST_LVL_RESETVAL (0x00000004u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REF_SSP_EN_MASK (0x20000000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REF_SSP_EN_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REF_SSP_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REF_USE_PAD_MASK (0x40000000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REF_USE_PAD_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REF_USE_PAD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REFCLKSEL_MASK (0x00180000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REFCLKSEL_SHIFT (0x00000013u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_REFCLKSEL_RESETVAL (0x00000002u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_RETENABLEN_MASK (0x00200000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_RETENABLEN_SHIFT (0x00000015u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_RETENABLEN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_SSC_EN_MASK (0x80000000u)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_SSC_EN_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_USB1_REG4_USB1_PHY_SSC_EN_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_USB1_REG4_RESETVAL   (0x89F0C000u)

/* usb1_reg5 */

#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_MPLL_MULTIPLIER_MASK (0x000FE000u)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_MPLL_MULTIPLIER_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_MPLL_MULTIPLIER_RESETVAL (0x00000019u)

#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_REF_CLKDIV2_MASK (0x00100000u)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_REF_CLKDIV2_SHIFT (0x00000014u)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_REF_CLKDIV2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_SSC_RANGE_MASK (0x00000007u)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_SSC_RANGE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_SSC_RANGE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_SSC_REF_CLK_SEL_MASK (0x00001FF0u)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_SSC_REF_CLK_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB1_REG5_USB1_PHY_SSC_REF_CLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_REG5_RESETVAL   (0x00032000u)

/* usb0_ebc_in_ctl */

#define CSL_BOOTCFG_USB0_EBC_IN_CTL_USB0_EBC14_SEL_MASK (0x00000030u)
#define CSL_BOOTCFG_USB0_EBC_IN_CTL_USB0_EBC14_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB0_EBC_IN_CTL_USB0_EBC14_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_EBC_IN_CTL_USB0_EBC15_SEL_MASK (0x00000003u)
#define CSL_BOOTCFG_USB0_EBC_IN_CTL_USB0_EBC15_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB0_EBC_IN_CTL_USB0_EBC15_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB0_EBC_IN_CTL_RESETVAL (0x00000000u)

/* usb1_ebc_in_ctl */

#define CSL_BOOTCFG_USB1_EBC_IN_CTL_USB1_EBC14_SEL_MASK (0x00000030u)
#define CSL_BOOTCFG_USB1_EBC_IN_CTL_USB1_EBC14_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_USB1_EBC_IN_CTL_USB1_EBC14_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_EBC_IN_CTL_USB1_EBC15_SEL_MASK (0x00000003u)
#define CSL_BOOTCFG_USB1_EBC_IN_CTL_USB1_EBC15_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_USB1_EBC_IN_CTL_USB1_EBC15_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_USB1_EBC_IN_CTL_RESETVAL (0x00000000u)

/* scratch00 */

#define CSL_BOOTCFG_SCRATCH00_SCRATCH_VAL00_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH00_SCRATCH_VAL00_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH00_SCRATCH_VAL00_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH00_RESETVAL   (0x00000000u)

/* scratch01 */

#define CSL_BOOTCFG_SCRATCH01_SCRATCH_VAL01_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH01_SCRATCH_VAL01_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH01_SCRATCH_VAL01_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH01_RESETVAL   (0x00000000u)

/* scratch02 */

#define CSL_BOOTCFG_SCRATCH02_SCRATCH_VAL02_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH02_SCRATCH_VAL02_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH02_SCRATCH_VAL02_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH02_RESETVAL   (0x00000000u)

/* scratch03 */

#define CSL_BOOTCFG_SCRATCH03_SCRATCH_VAL03_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH03_SCRATCH_VAL03_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH03_SCRATCH_VAL03_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH03_RESETVAL   (0x00000000u)

/* scratch04 */

#define CSL_BOOTCFG_SCRATCH04_SCRATCH_VAL04_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH04_SCRATCH_VAL04_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH04_SCRATCH_VAL04_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH04_RESETVAL   (0x00000000u)

/* scratch05 */

#define CSL_BOOTCFG_SCRATCH05_SCRATCH_VAL05_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH05_SCRATCH_VAL05_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH05_SCRATCH_VAL05_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH05_RESETVAL   (0x00000000u)

/* scratch06 */

#define CSL_BOOTCFG_SCRATCH06_SCRATCH_VAL06_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH06_SCRATCH_VAL06_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH06_SCRATCH_VAL06_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH06_RESETVAL   (0x00000000u)

/* scratch07 */

#define CSL_BOOTCFG_SCRATCH07_SCRATCH_VAL07_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH07_SCRATCH_VAL07_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH07_SCRATCH_VAL07_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH07_RESETVAL   (0x00000000u)

/* scratch08 */

#define CSL_BOOTCFG_SCRATCH08_SCRATCH_VAL08_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH08_SCRATCH_VAL08_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH08_SCRATCH_VAL08_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH08_RESETVAL   (0x00000000u)

/* scratch09 */

#define CSL_BOOTCFG_SCRATCH09_SCRATCH_VAL09_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH09_SCRATCH_VAL09_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH09_SCRATCH_VAL09_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH09_RESETVAL   (0x00000000u)

/* scratch10 */

#define CSL_BOOTCFG_SCRATCH10_SCRATCH_VAL10_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH10_SCRATCH_VAL10_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH10_SCRATCH_VAL10_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH10_RESETVAL   (0x00000000u)

/* scratch11 */

#define CSL_BOOTCFG_SCRATCH11_SCRATCH_VAL11_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH11_SCRATCH_VAL11_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH11_SCRATCH_VAL11_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH11_RESETVAL   (0x00000000u)

/* scratch12 */

#define CSL_BOOTCFG_SCRATCH12_SCRATCH_VAL12_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH12_SCRATCH_VAL12_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH12_SCRATCH_VAL12_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH12_RESETVAL   (0x00000000u)

/* scratch13 */

#define CSL_BOOTCFG_SCRATCH13_SCRATCH_VAL13_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH13_SCRATCH_VAL13_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH13_SCRATCH_VAL13_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH13_RESETVAL   (0x00000000u)

/* scratch14 */

#define CSL_BOOTCFG_SCRATCH14_SCRATCH_VAL14_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH14_SCRATCH_VAL14_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH14_SCRATCH_VAL14_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH14_RESETVAL   (0x00000000u)

/* scratch15 */

#define CSL_BOOTCFG_SCRATCH15_SCRATCH_VAL15_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_SCRATCH15_SCRATCH_VAL15_SHIFT (0x00000000u)
#define CSL_BOOTCFG_SCRATCH15_SCRATCH_VAL15_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_SCRATCH15_RESETVAL   (0x00000000u)

/* dsp_sec_stat */

#define CSL_BOOTCFG_DSP_SEC_STAT_DSP_SECURE_STAT0_MASK (0x00000001u)
#define CSL_BOOTCFG_DSP_SEC_STAT_DSP_SECURE_STAT0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DSP_SEC_STAT_DSP_SECURE_STAT0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DSP_SEC_STAT_RESETVAL (0x00000000u)

/* dsp_sec_en0 */

#define CSL_BOOTCFG_DSP_SEC_EN0_DSP_SEC_ENABLE_MASK (0x00000001u)
#define CSL_BOOTCFG_DSP_SEC_EN0_DSP_SEC_ENABLE_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DSP_SEC_EN0_DSP_SEC_ENABLE_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_DSP_SEC_EN0_RESETVAL (0x00000001u)

/* dsp_bootaddr0_ns */

#define CSL_BOOTCFG_DSP_BOOTADDR0_NS_DSP_NS_BOOTADDR_MASK (0xFFFFFC00u)
#define CSL_BOOTCFG_DSP_BOOTADDR0_NS_DSP_NS_BOOTADDR_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_DSP_BOOTADDR0_NS_DSP_NS_BOOTADDR_RESETVAL (0x00082C00u)

#define CSL_BOOTCFG_DSP_BOOTADDR0_NS_RESETVAL (0x20B00000u)

/* led_core_passdone0 */

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D0_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D1_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D2_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D2_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D3_MASK (0x00002000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D3_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D4_MASK (0x00020000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D4_SHIFT (0x00000011u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D5_MASK (0x00200000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D5_SHIFT (0x00000015u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D6_MASK (0x02000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D6_SHIFT (0x00000019u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D7_MASK (0x20000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D7_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_D7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I0_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I0_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I1_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I1_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I2_MASK (0x00000400u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I3_MASK (0x00004000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I3_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I4_MASK (0x00040000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I4_SHIFT (0x00000012u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I5_MASK (0x00400000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I5_SHIFT (0x00000016u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I6_MASK (0x04000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I6_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I7_MASK (0x40000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I7_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_I7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L0_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L0_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L1_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L1_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L2_MASK (0x00000800u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L2_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L3_MASK (0x00008000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L3_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L4_MASK (0x00080000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L4_SHIFT (0x00000013u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L5_MASK (0x00800000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L5_SHIFT (0x00000017u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L6_MASK (0x08000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L6_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L7_MASK (0x80000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L7_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_L7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P0_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P1_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P2_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P2_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P3_MASK (0x00001000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P3_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P4_MASK (0x00010000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P4_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P5_MASK (0x00100000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P5_SHIFT (0x00000014u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P6_MASK (0x01000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P6_SHIFT (0x00000018u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P7_MASK (0x10000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P7_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE0_PASSDONE0_P7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE0_RESETVAL (0x00000000u)

/* led_core_passdone1 */

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D0_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D0_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D1_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D1_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D2_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D2_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D3_MASK (0x00002000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D3_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D4_MASK (0x00020000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D4_SHIFT (0x00000011u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D5_MASK (0x00200000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D5_SHIFT (0x00000015u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D6_MASK (0x02000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D6_SHIFT (0x00000019u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D7_MASK (0x20000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D7_SHIFT (0x0000001Du)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_D7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I0_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I0_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I1_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I1_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I2_MASK (0x00000400u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I2_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I3_MASK (0x00004000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I3_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I4_MASK (0x00040000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I4_SHIFT (0x00000012u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I5_MASK (0x00400000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I5_SHIFT (0x00000016u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I6_MASK (0x04000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I6_SHIFT (0x0000001Au)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I7_MASK (0x40000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I7_SHIFT (0x0000001Eu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_I7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L0_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L0_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L1_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L1_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L2_MASK (0x00000800u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L2_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L3_MASK (0x00008000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L3_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L4_MASK (0x00080000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L4_SHIFT (0x00000013u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L5_MASK (0x00800000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L5_SHIFT (0x00000017u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L6_MASK (0x08000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L6_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L7_MASK (0x80000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L7_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_L7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P0_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P1_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P1_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P2_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P2_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P3_MASK (0x00001000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P3_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P3_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P4_MASK (0x00010000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P4_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P4_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P5_MASK (0x00100000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P5_SHIFT (0x00000014u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P5_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P6_MASK (0x01000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P6_SHIFT (0x00000018u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P6_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P7_MASK (0x10000000u)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P7_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_LED_CORE_PASSDONE1_PASSDONE1_P7_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CORE_PASSDONE1_RESETVAL (0x00000000u)

/* led_arm_bootaddr */

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_MASK (0xFFFFFF00u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_LED_ARM_BOOTADDR_RESETVAL (0x000000C4u)

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_ARM_LED_SELECT_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_ARM_LED_SELECT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_ARM_BOOTADDR_ARM_LED_SELECT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_ARM_BOOTADDR_RESETVAL (0x0000C400u)

/* led_gpio_clr */


#define CSL_BOOTCFG_LED_GPIO_CLR_RESETVAL (0x00000000u)

/* led_gpio_clr1 */

#define CSL_BOOTCFG_LED_GPIO_CLR1_RESETVAL (0x00000000u)

/* led_gpio */


#define CSL_BOOTCFG_LED_GPIO_RESETVAL    (0x00000000u)

/* led_gpio1 */

#define CSL_BOOTCFG_LED_GPIO1_RESETVAL   (0x00000000u)

/* led_plllock0 */

#define CSL_BOOTCFG_LED_PLLLOCK0_RESETVAL (0x00000000u)

/* led_plllock1 */

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM0_CODE_LOADED_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM0_CODE_LOADED_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM0_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM0_EXE_OK_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM0_EXE_OK_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM0_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM1_CODE_LOADED_MASK (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM1_CODE_LOADED_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM1_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM1_EXE_OK_MASK (0x00000008u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM1_EXE_OK_SHIFT (0x00000003u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM1_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM2_CODE_LOADED_MASK (0x00000010u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM2_CODE_LOADED_SHIFT (0x00000004u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM2_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM2_EXE_OK_MASK (0x00000020u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM2_EXE_OK_SHIFT (0x00000005u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM2_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM3_CODE_LOADED_MASK (0x00000040u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM3_CODE_LOADED_SHIFT (0x00000006u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM3_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM3_EXE_OK_MASK (0x00000080u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM3_EXE_OK_SHIFT (0x00000007u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM3_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM4_CODE_LOADED_MASK (0x00000100u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM4_CODE_LOADED_SHIFT (0x00000008u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM4_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM4_EXE_OK_MASK (0x00000200u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM4_EXE_OK_SHIFT (0x00000009u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM4_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM5_CODE_LOADED_MASK (0x00000400u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM5_CODE_LOADED_SHIFT (0x0000000Au)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM5_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM5_EXE_OK_MASK (0x00000800u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM5_EXE_OK_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM5_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM6_CODE_LOADED_MASK (0x00001000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM6_CODE_LOADED_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM6_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM6_EXE_OK_MASK (0x00002000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM6_EXE_OK_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM6_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM7_CODE_LOADED_MASK (0x00004000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM7_CODE_LOADED_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM7_CODE_LOADED_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM7_EXE_OK_MASK (0x00008000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM7_EXE_OK_SHIFT (0x0000000Fu)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM7_EXE_OK_RESETVAL (0x00000001u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM_GENERAL_MASK (0x1FFF0000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM_GENERAL_SHIFT (0x00000010u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM_GENERAL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_GEM_SUSP_CTL_MASK (0x80000000u)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM_SUSP_CTL_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_LED_PLLLOCK1_GEM_SUSP_CTL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_PLLLOCK1_RESETVAL (0x0000AAAAu)

/* led_chip_passdone */

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_MASK (0x00000002u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_SHIFT (0x00000001u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_DONE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_MASK (0x00000001u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_SHIFT (0x00000000u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_CHIP_PASS_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_MASK (0xFFFFFFFCu)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_SHIFT (0x00000002u)
#define CSL_BOOTCFG_LED_CHIP_PASSDONE_LED_CHIP_PASSDONE_RSVD_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_LED_CHIP_PASSDONE_RESETVAL (0x00000000u)

/* tdiode */

#define CSL_BOOTCFG_TDIODE_TDIODE_MASK   (0xFFFFFFFFu)
#define CSL_BOOTCFG_TDIODE_TDIODE_SHIFT  (0x00000000u)
#define CSL_BOOTCFG_TDIODE_TDIODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_TDIODE_RESETVAL      (0x00000000u)

/* margin0 */

#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_MASK (0x80000000u)
#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_SHIFT (0x0000001Fu)
#define CSL_BOOTCFG_MARGIN0_BTCFG_MARGIN_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN0_DFTWRITE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN0_RESETVAL     (0x00000000u)

/* margin1 */

#define CSL_BOOTCFG_MARGIN1_DFTWRITE1_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN1_DFTWRITE1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN1_DFTWRITE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN1_RESETVAL     (0x00000000u)

/* margin2 */

#define CSL_BOOTCFG_MARGIN2_DFTREAD0_MASK (0x00FFFFFFu)
#define CSL_BOOTCFG_MARGIN2_DFTREAD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_MARGIN2_DFTREAD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_MARGIN2_RESETVAL     (0x00000000u)

/* efuse_secrom_chksum0 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_EFUSE_SECROM_CHKSUM0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_EFUSE_SECROM_CHKSUM0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_EFUSE_SECROM_CHKSUM0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM0_RESETVAL (0x00000000u)

/* efuse_secrom_chksum1 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_EFUSE_SECROM_CHKSUM1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_EFUSE_SECROM_CHKSUM1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_EFUSE_SECROM_CHKSUM1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM1_RESETVAL (0x00000000u)

/* efuse_secrom_chksum2 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM2_RESETVAL (0x00000000u)

/* efuse_secrom_chksum3 */

#define CSL_BOOTCFG_EFUSE_SECROM_CHKSUM3_RESETVAL (0x00000000u)

/* int_spare0 */

#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_MASK (0x000000F0u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_SHIFT (0x00000004u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_DONE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_MASK (0x00000F00u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_SHIFT (0x00000008u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_AUTOLOAD_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_MASK (0x00001000u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_INT_SPARE0_EFC_ERR_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_MASK (0x00002000u)
#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_INT_SPARE0_EFC_INFO_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_INT_SPARE0_MASK (0xFFFFC000u)
#define CSL_BOOTCFG_INT_SPARE0_INT_SPARE0_SHIFT (0x0000000Eu)
#define CSL_BOOTCFG_INT_SPARE0_INT_SPARE0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_MASK (0x0000000Fu)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_SPARE0_SERDES_TEST_SELECT_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE0_RESETVAL  (0x00000000u)

/* int_spare1 */

#define CSL_BOOTCFG_INT_SPARE1_INT_SPARE1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_INT_SPARE1_INT_SPARE1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_INT_SPARE1_INT_SPARE1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_INT_SPARE1_RESETVAL  (0x00000000u)

/* chip_misc1 */

#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_EMIF4F_PSC_LOCK_N_MASK (0x00000800u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_EMIF4F_PSC_LOCK_N_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_EMIF4F_PSC_LOCK_N_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2ACS_LAT_MASK (0x00000780u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2ACS_LAT_SHIFT (0x00000007u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2ACS_LAT_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2RDLAT_MASK (0x00000078u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2RDLAT_SHIFT (0x00000003u)
#define CSL_BOOTCFG_CHIP_MISC1_CHIP_MISC_GEM_L2RDLAT_RESETVAL (0x00000003u)

#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PBIST_ENABLE_MASK (0x00001000u)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PBIST_ENABLE_SHIFT (0x0000000Cu)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PBIST_ENABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_MASK (0x00002000u)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_SHIFT (0x0000000Du)
#define CSL_BOOTCFG_CHIP_MISC1_TETRIS_PLL_ENABLE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_CHIP_MISC1_RESETVAL  (0x00000198u)

/* obsclk_ctl */

#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_MASK (0x00000002u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_SEL_MASK (0x00000001u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_SEL_SHIFT (0x00000000u)
#define CSL_BOOTCFG_OBSCLK_CTL_CORE_PLL_OBSCLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_EN_MASK (0x00000008u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_EN_SHIFT (0x00000003u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_SEL_MASK (0x00000004u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_SEL_SHIFT (0x00000002u)
#define CSL_BOOTCFG_OBSCLK_CTL_DDR3_PLL_OBSCLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_MASK (0x00000020u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_SHIFT (0x00000005u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_EN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_SEL_MASK (0x00000010u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_SEL_SHIFT (0x00000004u)
#define CSL_BOOTCFG_OBSCLK_CTL_PA_PLL_OBSCLK_SEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_OBSCLK_CTL_RESETVAL  (0x00000000u)

/* chip_misc3 */

#define CSL_BOOTCFG_CHIP_MISC3_RESETVAL  (0x00000000u)

/* efuse_rsvd0 */

#define CSL_BOOTCFG_EFUSE_RSVD0_EFUSE_RSVD0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD0_EFUSE_RSVD0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD0_EFUSE_RSVD0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD0_RESETVAL (0x00000000u)

/* efuse_rsvd1 */

#define CSL_BOOTCFG_EFUSE_RSVD1_EFUSE_RSVD1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD1_EFUSE_RSVD1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD1_EFUSE_RSVD1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD1_RESETVAL (0x00000000u)

/* efuse_rsvd2 */

#define CSL_BOOTCFG_EFUSE_RSVD2_EFUSE_RSVD2_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_EFUSE_RSVD2_EFUSE_RSVD2_SHIFT (0x00000000u)
#define CSL_BOOTCFG_EFUSE_RSVD2_EFUSE_RSVD2_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_EFUSE_RSVD2_RESETVAL (0x00000000u)

/* efuse_rsvd3 */

#define CSL_BOOTCFG_EFUSE_RSVD3_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode0_0 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE0_0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE0_0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_PWRSWTCH_WKUP_MODE0_0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_0_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode0_1 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE0_1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE0_1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_PWRSWTCH_WKUP_MODE0_1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE0_1_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode1_0 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE1_0_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE1_0_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_PWRSWTCH_WKUP_MODE1_0_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_0_RESETVAL (0x00000000u)

/* pwrswtch_wkup_mode1_1 */

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE1_1_MASK (0xFFFFFFFFu)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE1_1_SHIFT (0x00000000u)
#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_PWRSWTCH_WKUP_MODE1_1_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_PWRSWTCH_WKUP_MODE1_1_RESETVAL (0x00000000u)

/* dft_usb0_utmi_control */

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TC_TEST_UTMI_MASK (0x00000001u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TC_TEST_UTMI_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TC_TEST_UTMI_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_DMPULLDOWN_MASK (0x00000002u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_DMPULLDOWN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_DMPULLDOWN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_DPPULLDOWN_MASK (0x00000004u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_DPPULLDOWN_SHIFT (0x00000002u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_DPPULLDOWN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_OPMODE_MASK (0x00000018u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_OPMODE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_OPMODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_SLEEPM_MASK (0x00000020u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_SLEEPM_SHIFT (0x00000005u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_SLEEPM_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_SUSPENDM_MASK (0x00000040u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_SUSPENDM_SHIFT (0x00000006u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_SUSPENDM_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TERMSEL_MASK (0x00000080u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TERMSEL_SHIFT (0x00000007u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TERMSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXDATA_MASK (0x0007F800u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXDATA_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXDATA_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXDATAH_MASK (0x07F80000u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXDATAH_SHIFT (0x00000013u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXDATAH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXVALID_MASK (0x08000000u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXVALID_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXVALID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXVALIDH_MASK (0x10000000u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXVALIDH_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_TXVALIDH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_WORDINTERFACE_MASK (0x00000100u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_WORDINTERFACE_SHIFT (0x00000008u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_WORDINTERFACE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_XCVRSEL_MASK (0x00000600u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_XCVRSEL_SHIFT (0x00000009u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_USB0_PHY_TU_XCVRSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_CONTROL_RESETVAL (0x00000000u)

/* dft_usb0_utmi_observe */

#define CSL_BOOTCFG_DFT_USB0_UTMI_OBSERVE_USB0_UTMI_RXDATA_MASK (0x000000FFu)
#define CSL_BOOTCFG_DFT_USB0_UTMI_OBSERVE_USB0_UTMI_RXDATA_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_OBSERVE_USB0_UTMI_RXDATA_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_OBSERVE_USB0_UTMI_RXDATAH_MASK (0x0000FF00u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_OBSERVE_USB0_UTMI_RXDATAH_SHIFT (0x00000008u)
#define CSL_BOOTCFG_DFT_USB0_UTMI_OBSERVE_USB0_UTMI_RXDATAH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB0_UTMI_OBSERVE_RESETVAL (0x00000000u)

/* dft_usb1_utmi_control */

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TC_TEST_UTMI_MASK (0x00000001u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TC_TEST_UTMI_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TC_TEST_UTMI_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_DMPULLDOWN_MASK (0x00000002u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_DMPULLDOWN_SHIFT (0x00000001u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_DMPULLDOWN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_DPPULLDOWN_MASK (0x00000004u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_DPPULLDOWN_SHIFT (0x00000002u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_DPPULLDOWN_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_OPMODE_MASK (0x00000018u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_OPMODE_SHIFT (0x00000003u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_OPMODE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_SLEEPM_MASK (0x00000020u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_SLEEPM_SHIFT (0x00000005u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_SLEEPM_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_SUSPENDM_MASK (0x00000040u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_SUSPENDM_SHIFT (0x00000006u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_SUSPENDM_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TERMSEL_MASK (0x00000080u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TERMSEL_SHIFT (0x00000007u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TERMSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXDATA_MASK (0x0007F800u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXDATA_SHIFT (0x0000000Bu)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXDATA_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXDATAH_MASK (0x07F80000u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXDATAH_SHIFT (0x00000013u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXDATAH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXVALID_MASK (0x08000000u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXVALID_SHIFT (0x0000001Bu)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXVALID_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXVALIDH_MASK (0x10000000u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXVALIDH_SHIFT (0x0000001Cu)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_TXVALIDH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_WORDINTERFACE_MASK (0x00000100u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_WORDINTERFACE_SHIFT (0x00000008u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_WORDINTERFACE_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_XCVRSEL_MASK (0x00000600u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_XCVRSEL_SHIFT (0x00000009u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_USB1_PHY_TU_XCVRSEL_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_CONTROL_RESETVAL (0x00000000u)

/* dft_usb1_utmi_observe */

#define CSL_BOOTCFG_DFT_USB1_UTMI_OBSERVE_USB1_UTMI_RXDATA_MASK (0x000000FFu)
#define CSL_BOOTCFG_DFT_USB1_UTMI_OBSERVE_USB1_UTMI_RXDATA_SHIFT (0x00000000u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_OBSERVE_USB1_UTMI_RXDATA_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_OBSERVE_USB1_UTMI_RXDATAH_MASK (0x0000FF00u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_OBSERVE_USB1_UTMI_RXDATAH_SHIFT (0x00000008u)
#define CSL_BOOTCFG_DFT_USB1_UTMI_OBSERVE_USB1_UTMI_RXDATAH_RESETVAL (0x00000000u)

#define CSL_BOOTCFG_DFT_USB1_UTMI_OBSERVE_RESETVAL (0x00000000u)

/* end_point */

#define CSL_BOOTCFG_END_POINT_RESETVAL   (0x00000000u)


#ifdef __cplusplus
}
#endif

#endif
